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Do not allow masked write in default case.

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This commit is contained in:
Lukas Steiner
2023-08-23 11:41:58 +02:00
parent 8c248e8e23
commit 0f824e8b92
26 changed files with 101 additions and 55 deletions
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2
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
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@@ -283,7 +283,7 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
}
}
bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
auto burstLength = ControllerExtension::getBurstLength(payload);

16
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
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@@ -119,17 +119,17 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalSB() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
[[nodiscard]] unsigned getRAADEC() const override;
[[nodiscard]] unsigned getRAAIMT() const override;
[[nodiscard]] unsigned getRAAMMT() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
};
} // namespace DRAMSys

12
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
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@@ -197,16 +197,4 @@ unsigned MemSpecHBM3::getRAAMMT() const
return RAAMMT;
}
bool MemSpecHBM3::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
{
bool maskedWrite = payload.get_byte_enable_ptr() != nullptr;
if (maskedWrite)
{
SC_REPORT_FATAL("MemSpecHBM3", "HBM3 does not support masked writes!");
}
return maskedWrite;
}
} // namespace DRAMSys

18
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
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@@ -89,19 +89,17 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAADEC() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
[[nodiscard]] unsigned getRAADEC() const override;
[[nodiscard]] unsigned getRAAIMT() const override;
[[nodiscard]] unsigned getRAAMMT() const override;
bool hasRasAndCasBus() const override;
[[nodiscard]] bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

5
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -248,4 +248,9 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
}
}
bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}
} // namespace DRAMSys

14
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
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@@ -111,14 +111,16 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalP2B() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
unsigned getPer2BankOffset() const override;
[[nodiscard]] unsigned getPer2BankOffset() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
private:
unsigned per2BankOffset;