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Additional check of byte enable pointer.

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This commit is contained in:
Lukas Steiner
2023-08-23 15:21:53 +02:00
parent 76e58b1755
commit 12f2b73cde
12 changed files with 34 additions and 16 deletions
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2
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
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@@ -290,7 +290,7 @@ bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
if (burstLength == 16 && bitWidth == 4)
return true;
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -250,7 +250,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

18
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -150,11 +150,27 @@ bool MemSpec::hasRasAndCasBus() const
bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
if (payload.get_byte_enable_ptr() == nullptr)
if (allBytesEnabled(payload))
return false;
SC_REPORT_FATAL("MemSpec", "Standard does not support masked writes!");
throw;
}
bool MemSpec::allBytesEnabled(const tlm::tlm_generic_payload& trans)
{
if (trans.get_byte_enable_ptr() == nullptr)
return true;
for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++)
{
if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED)
{
return false;
}
}
return true;
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -118,6 +118,8 @@ protected:
unsigned banksPerChannel, unsigned bankGroupsPerChannel,
unsigned devicesPerRank);
[[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans);
MemSpec(const MemSpec &) = default;
MemSpec(MemSpec &&) = default;

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
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@@ -170,7 +170,7 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unuse
bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
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@@ -188,7 +188,7 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unuse
bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
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@@ -177,7 +177,7 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unuse
bool MemSpecHBM2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -183,7 +183,7 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unu
bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
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@@ -143,7 +143,7 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_un
bool MemSpecSTTMRAM::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
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@@ -175,7 +175,7 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unu
bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
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@@ -165,7 +165,7 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_un
bool MemSpecWideIO2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
return !allBytesEnabled(payload);
}
} // namespace DRAMSys

12
src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
View File

@@ -154,7 +154,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
trans.get_data_ptr()[i] = phyAddr[i];
}
@@ -174,7 +174,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
phyAddr[i] = trans.get_data_ptr()[i];
}
@@ -215,7 +215,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
trans.get_data_ptr()[i] = phyAddr[i];
}
@@ -243,7 +243,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
phyAddr[i] = trans.get_data_ptr()[i];
}
@@ -286,7 +286,7 @@ void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& del
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
trans.get_data_ptr()[i] = phyAddr[i];
}
@@ -304,7 +304,7 @@ void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& del
for (std::size_t i = 0; i < trans.get_data_length(); i++)
{
std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
{
phyAddr[i] = trans.get_data_ptr()[i];
}