diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
index 605f0176..76b1b02c 100644
--- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
+++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
@@ -290,7 +290,7 @@ bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
     if (burstLength == 16 && bitWidth == 4)
         return true;
 
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
index 9d175a72..67ff9f18 100644
--- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
+++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
@@ -250,7 +250,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
 
 bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
index 420e63c9..2c9dc0a1 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
@@ -150,11 +150,27 @@ bool MemSpec::hasRasAndCasBus() const
 
 bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    if (payload.get_byte_enable_ptr() == nullptr)
+    if (allBytesEnabled(payload))
         return false;
 
     SC_REPORT_FATAL("MemSpec", "Standard does not support masked writes!");
     throw;
 }
 
+bool MemSpec::allBytesEnabled(const tlm::tlm_generic_payload& trans)
+{
+    if (trans.get_byte_enable_ptr() == nullptr)
+        return true;
+
+    for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++)
+    {
+        if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED)
+        {
+            return false;
+        }
+    }
+
+    return true;
+}
+
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
index e97d2e2f..31ab977c 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
@@ -118,6 +118,8 @@ protected:
         unsigned banksPerChannel, unsigned bankGroupsPerChannel,
         unsigned devicesPerRank);
 
+    [[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans);
+
     MemSpec(const MemSpec &) = default;
     MemSpec(MemSpec &&) = default;
 
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
index 472997f4..9f486e65 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
@@ -170,7 +170,7 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unuse
 
 bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
index 0f109964..5e09d024 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
@@ -188,7 +188,7 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unuse
 
 bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
index 2bc529c1..83035450 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
@@ -177,7 +177,7 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unuse
 
 bool MemSpecHBM2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
index 251ab31c..7a97b67d 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
@@ -183,7 +183,7 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unu
 
 bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
index 4a46edcd..037d0e49 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
@@ -143,7 +143,7 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_un
 
 bool MemSpecSTTMRAM::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
index 796c63e2..cb4b5289 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
@@ -175,7 +175,7 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unu
 
 bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
index 560ae295..533665e4 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
@@ -165,7 +165,7 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_un
 
 bool MemSpecWideIO2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    return !allBytesEnabled(payload);
 }
 
 } // namespace DRAMSys
diff --git a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
index 46a772cc..0ca2ecf7 100644
--- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
+++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
@@ -154,7 +154,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
                 for (std::size_t i = 0; i < trans.get_data_length(); i++)
                 {
                     std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                     {
                         trans.get_data_ptr()[i] = phyAddr[i];
                     }
@@ -174,7 +174,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
                 for (std::size_t i = 0; i < trans.get_data_length(); i++)
                 {
                     std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                     {
                         phyAddr[i] = trans.get_data_ptr()[i];
                     }
@@ -215,7 +215,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
                     for (std::size_t i = 0; i < trans.get_data_length(); i++)
                     {
                         std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                        if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                        if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                         {
                             trans.get_data_ptr()[i] = phyAddr[i];
                         }
@@ -243,7 +243,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
                     for (std::size_t i = 0; i < trans.get_data_length(); i++)
                     {
                         std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                        if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                        if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                         {
                             phyAddr[i] = trans.get_data_ptr()[i];
                         }
@@ -286,7 +286,7 @@ void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& del
                 for (std::size_t i = 0; i < trans.get_data_length(); i++)
                 {
                     std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                     {
                         trans.get_data_ptr()[i] = phyAddr[i];
                     }
@@ -304,7 +304,7 @@ void Dram::b_transport(tlm_generic_payload& trans, [[maybe_unused]] sc_time& del
                 for (std::size_t i = 0; i < trans.get_data_length(); i++)
                 {
                     std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
-                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] == TLM_BYTE_ENABLED)
                     {
                         phyAddr[i] = trans.get_data_ptr()[i];
                     }