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Add hack in TimingCheckers to convert MWR to WR in insertion stage

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This commit is contained in:
Derek Christ
2023-08-15 10:56:44 +02:00
parent f7066a22b0
commit 40dbc518b6
15 changed files with 88 additions and 4 deletions
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8
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -281,7 +281,13 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
{
assert(false); // TODO
// auto burstLength = ControllerExtension::getBurstLength(payload);
// if (burstLength == 16 && bitWidth == 4)
// return true;
// assert(false); // TODO
return payload.get_byte_enable_ptr() != nullptr;
}

6
extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
View File

@@ -950,6 +950,12 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
+ static_cast<std::size_t>(bank) % memSpec->banksPerGroup);
unsigned burstLength = ControllerExtension::getBurstLength(payload);
// Hack: Convert MWR to WR and MWRA to WRA
if (command == Command::MWR)
command = Command::WR;
else if (command == Command::MWRA)
command = Command::WRA;
PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
+ " command is " + command.toString());

6
extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp
View File

@@ -733,6 +733,12 @@ void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload)
BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
Bank bank = ControllerExtension::getBank(payload);
// Hack: Convert MWR to WR and MWRA to WRA
if (command == Command::MWR)
command = Command::WR;
else if (command == Command::MWRA)
command = Command::WRA;
PRINTDEBUGMESSAGE("CheckerHBM3", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
+ " command is " + command.toString());

2
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -250,7 +250,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
bool MemSpecLPDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
{
assert(false); // TODO
// assert(false); // TODO
return payload.get_byte_enable_ptr() != nullptr;
}

6
extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp
View File

@@ -730,6 +730,12 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload)
Bank bank = ControllerExtension::getBank(payload);
unsigned burstLength = ControllerExtension::getBurstLength(payload);
// Hack: Convert MWR to WR and MWRA to WRA
if (command == Command::MWR)
command = Command::WR;
else if (command == Command::MWRA)
command = Command::WRA;
PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
+ " command is " + command.toString());