From 40dbc518b60afdf1ce0f9cc799e9654a426fdc22 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Tue, 15 Aug 2023 10:56:44 +0200 Subject: [PATCH] Add hack in TimingCheckers to convert MWR to WR in insertion stage --- .../DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp | 8 +++++++- .../DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp | 6 ++++++ .../HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp | 6 ++++++ .../DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp | 2 +- .../LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp | 6 ++++++ src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp | 6 ++++++ src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp | 6 ++++++ .../DRAMSys/controller/checker/CheckerGDDR5.cpp | 8 +++++++- .../DRAMSys/controller/checker/CheckerGDDR5X.cpp | 8 +++++++- .../DRAMSys/controller/checker/CheckerGDDR6.cpp | 6 ++++++ src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp | 6 ++++++ .../DRAMSys/controller/checker/CheckerLPDDR4.cpp | 6 ++++++ .../DRAMSys/controller/checker/CheckerSTTMRAM.cpp | 6 ++++++ .../DRAMSys/controller/checker/CheckerWideIO.cpp | 6 ++++++ .../DRAMSys/controller/checker/CheckerWideIO2.cpp | 6 ++++++ 15 files changed, 88 insertions(+), 4 deletions(-) diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index 9446cb7e..ecd07d8a 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -281,7 +281,13 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const { - assert(false); // TODO + // auto burstLength = ControllerExtension::getBurstLength(payload); + + // if (burstLength == 16 && bitWidth == 4) + // return true; + + // assert(false); // TODO + return payload.get_byte_enable_ptr() != nullptr; } diff --git a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp index c25e549e..153a39a9 100644 --- a/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp @@ -950,6 +950,12 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload) + static_cast(bank) % memSpec->banksPerGroup); unsigned burstLength = ControllerExtension::getBurstLength(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp index d9d3fde4..4b627229 100644 --- a/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp @@ -733,6 +733,12 @@ void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerHBM3", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 05fe2990..154b78d9 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -250,7 +250,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g bool MemSpecLPDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const { - assert(false); // TODO + // assert(false); // TODO return payload.get_byte_enable_ptr() != nullptr; } diff --git a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp index 955bded6..cbece361 100644 --- a/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp @@ -730,6 +730,12 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload) Bank bank = ControllerExtension::getBank(payload); unsigned burstLength = ControllerExtension::getBurstLength(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp index 1f00e8c5..48b51ae1 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp @@ -433,6 +433,12 @@ void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload) Rank rank = ControllerExtension::getRank(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp index db410aad..be50f739 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp @@ -467,6 +467,12 @@ void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp index 685ae2f6..b6258fcf 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp @@ -53,7 +53,7 @@ CheckerGDDR5::CheckerGDDR5(const Configuration& config) lastScheduledByCommandAndBank = std::vector> (Command::numberOfCommands(), ControllerVector(memSpec->banksPerChannel, scMaxTime)); lastScheduledByCommandAndBankGroup = std::vector> - (Command::numberOfCommands(), + (Command::numberOfCommands(), ControllerVector(memSpec->bankGroupsPerChannel, scMaxTime)); lastScheduledByCommandAndRank = std::vector> (Command::numberOfCommands(), ControllerVector(memSpec->ranksPerChannel, scMaxTime)); @@ -549,6 +549,12 @@ void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp index 063463df..f2f1d283 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp @@ -53,7 +53,7 @@ CheckerGDDR5X::CheckerGDDR5X(const Configuration& config) lastScheduledByCommandAndBank = std::vector> (Command::numberOfCommands(), ControllerVector(memSpec->banksPerChannel, scMaxTime)); lastScheduledByCommandAndBankGroup = std::vector> - (Command::numberOfCommands(), + (Command::numberOfCommands(), ControllerVector(memSpec->bankGroupsPerChannel, scMaxTime)); lastScheduledByCommandAndRank = std::vector> (Command::numberOfCommands(), ControllerVector(memSpec->ranksPerChannel, scMaxTime)); @@ -553,6 +553,12 @@ void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp index 396f5c50..f86d71f2 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp @@ -570,6 +570,12 @@ void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp index 0b9f6770..3969fd84 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp @@ -502,6 +502,12 @@ void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload) BankGroup bankGroup = ControllerExtension::getBankGroup(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index 813cad39..b6667e66 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -521,6 +521,12 @@ void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload) Rank rank = ControllerExtension::getRank(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp index faba3563..ff1535bd 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp @@ -389,6 +389,12 @@ void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload) Rank rank = ControllerExtension::getRank(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp index ca60076a..a9912809 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp @@ -410,6 +410,12 @@ void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload) Rank rank = ControllerExtension::getRank(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString()); diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp index 0ca3e8df..aa1c54cf 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp @@ -488,6 +488,12 @@ void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload) Rank rank = ControllerExtension::getRank(payload); Bank bank = ControllerExtension::getBank(payload); + // Hack: Convert MWR to WR and MWRA to WRA + if (command == Command::MWR) + command = Command::WR; + else if (command == Command::MWRA) + command = Command::WRA; + PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(static_cast(bank)) + " command is " + command.toString());