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65f5f61ca8cf1dfedcb0835c5e1ecf0d78df8177
gem5/src/arch/arm
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Gabe Black 65f5f61ca8 fastmodel: Adopt the default implementations of TC *Reg funcs. 
The ThreadContext methods for the fast model are not on the critical
path and so aren't performance sensitive, and this will avoid having to
reorganize the readIntReg, etc, functions to use the new scheme. That
can be done down the line.

Change-Id: Icb9196815ce5a07edae333f19d2ea120015aaf1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49112
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-02-10 23:58:45 +00:00
..
fastmodel
fastmodel: Adopt the default implementations of TC *Reg funcs.
2022-02-10 23:58:45 +00:00
freebsd
arch,sim-se: Handle syscall retry/suppression in the syscall desc.
2021-12-13 20:31:51 +00:00
gdb-xml
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
insts
arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs.
2021-12-03 03:05:41 +00:00
isa
arch-arm: Replace MISCREG_CP14/15_UNIMPL with MISCREG_UNKNOWN
2022-02-07 09:45:50 +00:00
kvm
arch-arm, kvm: Handle vcpu2 if more than 256 vCPUs are in use
2022-02-10 08:59:25 +00:00
linux
arch-arm: Add support for initrd/initramfs
2022-01-05 21:38:34 +00:00
regs
arch-arm: Generate a decode map for AArch32 MiscRegs
2022-02-08 09:15:55 +00:00
tracers
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
aapcs32.hh
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
aapcs64.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
aapcs64.test.cc
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
ArmCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
ArmDecoder.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
ArmFsWorkload.py
arch-arm: Add support for initrd/initramfs
2022-01-05 21:38:34 +00:00
ArmInterrupts.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ArmISA.py
arch-arm,cpu: Replace rename modes with split reg/elem register files.
2021-10-28 06:00:07 +00:00
ArmMMU.py
arch-arm: Allow the L2 unified TLB to store partial translations
2021-12-12 05:04:24 +00:00
ArmNativeTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ArmPMU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ArmSemihosting.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ArmSeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ArmSystem.py
arch-arm: Add an Armv8.4 ArmRelease object
2021-09-30 16:03:41 +00:00
ArmTLB.py
arch-arm: Allow TLB to be used as a WalkCache
2021-12-12 05:04:24 +00:00
AtomicSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decoder.cc
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
decoder.hh
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
faults.cc
arch,sim-se: Update the PC before emulating a system call.
2021-12-12 00:29:53 +00:00
faults.hh
arch-arm,arch-sparc: Remove legacy stat for faults
2021-12-07 15:03:38 +00:00
fs_workload.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
fs_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
htm.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
htm.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa.cc
cpu,arch-arm: Track register size in RegClassInfo.
2022-02-04 12:12:37 +00:00
isa.hh
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
MinorCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
mmu.cc
arch-arm: Allowing table descriptor to be inserted in TLB
2021-12-12 05:04:24 +00:00
mmu.hh
arch-arm: Allow TLB to be used as a WalkCache
2021-12-12 05:04:24 +00:00
nativetrace.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
NonCachingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3Checker.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.cc
arch-arm: Add walkBits method to PageTableOps
2021-10-27 09:05:44 +00:00
pagetable.hh
arch-arm: Add partial param to TlbEntry
2021-12-10 16:09:09 +00:00
pauth_helpers.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pauth_helpers.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Make branching() a virtual member of PCStateBase.
2021-11-30 23:30:06 +00:00
pmu.cc
arch-arm, dev-arm: Add currEL function to the ISA class
2021-12-07 18:58:49 +00:00
pmu.hh
arch-arm: Fix memory leak of PMU events
2021-09-22 05:31:01 +00:00
process.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
qarma.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
qarma.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
remote_gdb.cc
arch-arm: gdb support Thumb-2 ISA
2021-12-16 13:26:45 +00:00
remote_gdb.hh
base: Correct checkBpLen naming with checkBpKind
2021-12-16 13:26:39 +00:00
SConscript
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
sim: Move the MemPools object out of System and into SEWorkload.
2021-09-30 00:30:49 +00:00
self_debug.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
self_debug.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
semihosting.cc
arch-arm: For semihosting, mask reg value and not index.
2021-08-31 23:45:00 +00:00
semihosting.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stage2_lookup.cc
arch-arm: Move translation logic from the ArmTLB to the ArmMMU
2021-07-28 08:13:09 +00:00
stage2_lookup.hh
arch-arm: Move translation logic from the ArmTLB to the ArmMMU
2021-07-28 08:13:09 +00:00
system.cc
arch-arm: Add missing Armv8.2 extensions to the enum
2021-09-30 16:03:41 +00:00
system.hh
misc: Remove include of arch/page_size.hh, and fix up includes.
2021-10-22 21:43:02 +00:00
table_walker.cc
arch-arm: Do not squash table walks if translation is partial
2021-12-14 09:43:41 +00:00
table_walker.hh
arch-arm: Allowing table descriptor to be inserted in TLB
2021-12-12 05:04:24 +00:00
TimingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
tlb.cc
arch-arm: Allow TLB to be used as a WalkCache
2021-12-12 05:04:24 +00:00
tlb.hh
arch-arm: Allow TLB to be used as a WalkCache
2021-12-12 05:04:24 +00:00
tlbi_op.cc
arch-arm: EL2&0 invalidations do not depend on VMID
2021-10-18 13:47:18 +00:00
tlbi_op.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
types.hh
arch-arm: Define an Affinity type
2022-02-03 16:36:29 +00:00
utility.cc
arch-arm: Define an Affinity type
2022-02-03 16:36:29 +00:00
utility.hh
arch-arm: Define an Affinity type
2022-02-03 16:36:29 +00:00
vecregs.hh
arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
2021-05-07 19:36:08 +00:00