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arch-arm: For semihosting, mask reg value and not index.

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In ArmSemihosting::call64, the *index* of X0 was masked to be 32 bits (a
noop), and then read using the TC, where I'm pretty sure what was
intended was to read the value and then mask what was returned.

Change-Id: I66cb845d4e97b1895072bd98de709256625c8e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49762
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-28 16:25:59 -07:00
parent cd27e47558
commit dd59da928d
1 changed files with 1 additions and 1 deletions
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2
src/arch/arm/semihosting.cc
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@@ -169,7 +169,7 @@ ArmSemihosting::ArmSemihosting(const ArmSemihostingParams &p)
bool
ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
RegVal op = tc->readIntReg(ArmISA::INTREG_X0) & mask(32);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi64>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);