arch-arm: Eliminate the INTREG_DUMMY integer register.

This register index was for an integer register which was just something
to return when the result should be thrown away. That's basically what
the zero register is/could already be used for. Replace INTREG_DUMMY
with INTREG_ZERO.

Also, change the type used for an index in SVE memory instructions from
IntRegIndex to RegIndex, since it's not actually storing an integer
register index, and g++ gets upset when you try to compare one against a
value which is out of range for that enum.

Change-Id: Ibdc488a2b55162a5f9e3d355126f6c48a99272a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49223
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa/insts/misc.isa

@@ -290,7 +290,7 @@ let {{
                 // you look at the generated C code you'll find that they are.
                 // However this is safe as DecodedBankedIntReg (which is used
                 // in operands.isa to get the index of DecodedBankedIntReg)
-                // will return INTREG_DUMMY if its not a valid integer
+                // will return INTREG_ZERO if its not a valid integer
                 // register, so redirecting the write to somewhere we don't
                 // care about.
                 DecodedBankedIntReg = Op1;

src/arch/arm/isa/templates/sve_mem.isa

@@ -890,7 +890,7 @@ def template SveStructMemSIMicroopDeclare {{
         typedef _Element Element;
         typedef _Element TPElem;
 
-        IntRegIndex dest;
+        RegIndex dest;
         IntRegIndex gp;
         IntRegIndex base;
         int64_t imm;
@@ -904,7 +904,7 @@ def template SveStructMemSIMicroopDeclare {{
 
       public:
         %(class_name)s(const char* mnem, ExtMachInst machInst,
-                IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+                RegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
                 int64_t _imm, uint8_t _numRegs, int _regIndex) :
             %(base_class)s(mnem, machInst, %(op_class)s),
             dest(_dest), gp(_gp), base(_base), imm(_imm),
@@ -1167,7 +1167,7 @@ def template SveStructMemSSMicroopDeclare {{
         typedef _Element Element;
         typedef _Element TPElem;
 
-        IntRegIndex dest;
+        RegIndex dest;
         IntRegIndex gp;
         IntRegIndex base;
         IntRegIndex offset;
@@ -1181,7 +1181,7 @@ def template SveStructMemSSMicroopDeclare {{
 
       public:
         %(class_name)s(const char* mnem, ExtMachInst machInst,
-                IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+                RegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
                 IntRegIndex _offset, uint8_t _numRegs, int _regIndex) :
             %(base_class)s(mnem, machInst, %(op_class)s),
             dest(_dest), gp(_gp), base(_base), offset(_offset),

src/arch/arm/regs/int.hh

@@ -127,7 +127,6 @@ enum IntRegIndex
     INTREG_UREG0,
     INTREG_UREG1,
     INTREG_UREG2,
-    INTREG_DUMMY, // Dummy reg used to throw away int reg results
 
     INTREG_SP0,
     INTREG_SP1,

src/arch/arm/utility.hh

@@ -372,7 +372,7 @@ decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
 
     validReg = decodeMrsMsrBankedReg(
             sysM, r, isIntReg, regIdx, 0, 0, 0, false);
-    return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
+    return (validReg && isIntReg) ? regIdx : INTREG_ZERO;
 }
 
 /**