From dd59da928da0f76f40d66f8798d309abcc516643 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Aug 2021 16:25:59 -0700 Subject: [PATCH] arch-arm: For semihosting, mask reg value and not index. In ArmSemihosting::call64, the *index* of X0 was masked to be 32 bits (a noop), and then read using the TC, where I'm pretty sure what was intended was to read the value and then mask what was returned. Change-Id: I66cb845d4e97b1895072bd98de709256625c8e3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49762 Reviewed-by: Andreas Sandberg Reviewed-by: Giacomo Travaglini Maintainer: Andreas Sandberg Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/semihosting.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc index fc98d6e9a4..ed6fa2970b 100644 --- a/src/arch/arm/semihosting.cc +++ b/src/arch/arm/semihosting.cc @@ -169,7 +169,7 @@ ArmSemihosting::ArmSemihosting(const ArmSemihostingParams &p) bool ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops) { - RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32)); + RegVal op = tc->readIntReg(ArmISA::INTREG_X0) & mask(32); if (op > MaxStandardOp && !gem5_ops) { unrecognizedCall( tc, "Gem5 semihosting op (0x%x) disabled from here.", op);