arch-arm: Add missing Armv8.2 extensions to the enum

Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51017
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2021-09-23 09:29:46 +01:00
parent d8c61b2e24
commit 10cbcb14e8
3 changed files with 22 additions and 3 deletions

View File

@@ -55,6 +55,9 @@ class ArmExtension(ScopedEnum):
# Armv8.2
'FEAT_SVE',
'FEAT_UAO',
'FEAT_LVA', # Optional in Armv8.2
'FEAT_LPA', # Optional in Armv8.2
# Armv8.4
'FEAT_SEL2',
@@ -100,8 +103,12 @@ class Armv8(ArmRelease):
class ArmDefaultRelease(Armv8):
extensions = Armv8.extensions + [
'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
# Armv8.1
'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
# Armv8.2
'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
# Armv8.4
'FEAT_SEL2'
]
class Armv81(Armv8):

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@@ -458,6 +458,16 @@ ISA::initID64(const ArmISAParams &p)
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
/** MISCREG_ID_AA64MMFR2_EL1 */
// UAO
miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR2_EL1], 7, 4,
release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
// LVA
miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR2_EL1], 19, 16,
release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
// TME
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(

View File

@@ -102,7 +102,9 @@ ArmSystem::ArmSystem(const Params &p)
if (_highestELIs64 && (
_physAddrRange64 < 32 ||
_physAddrRange64 > MaxPhysAddrRange ||
(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42) ||
(_physAddrRange64 == 52 && !release->has(ArmExtension::FEAT_LPA))))
{
fatal("Invalid physical address range (%d)\n", _physAddrRange64);
}
}