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Commit Graph

  • f64c8bafd2 ARM: BXJ should be BX when there is no J support Ali Saidi 2010-06-02 12:58:12 -05:00
  • 1fcd389fa3 ARM: Make sure macroops aren't interrupted midinstruction. Gabe Black 2010-06-02 12:58:12 -05:00
  • 67766cbf17 ARM: Fix the implementation of the VFP ldm and stm macroops. Gabe Black 2010-06-02 12:58:12 -05:00
  • d149e43c41 Simple CPU: Make the FloatRegs trace flag do something. Gabe Black 2010-06-02 12:58:12 -05:00
  • ad9c5af945 ARM: Fix up thumb decoding of coproc instructions. Gabe Black 2010-06-02 12:58:12 -05:00
  • dea707704f ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC. Gabe Black 2010-06-02 12:58:12 -05:00
  • b504b44b2f CPU: Reset fetch offset after a exception Ali Saidi 2010-06-02 12:58:12 -05:00
  • 943b77b9bb ARM: Decode the VLDR instruction. Gabe Black 2010-06-02 12:58:12 -05:00
  • 4f130683e0 ARM: Implement the VLDR instruction. Gabe Black 2010-06-02 12:58:12 -05:00
  • dbec303864 ARM: Decode all the various forms of vmov. Gabe Black 2010-06-02 12:58:12 -05:00
  • ff3996b24d ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11. Gabe Black 2010-06-02 12:58:12 -05:00
  • dd1aedc98b ARM: Implement the various versions of VMOV. Gabe Black 2010-06-02 12:58:12 -05:00
  • 1f059541d6 ARM: Add a new RegImmOp base class. Gabe Black 2010-06-02 12:58:12 -05:00
  • 6976b4890a ARM: Add a RegRegImmOp base class. Gabe Black 2010-06-02 12:58:12 -05:00
  • 186cfe3ae3 ARM: Widen the immediate fields in the misc instruction classes. Gabe Black 2010-06-02 12:58:12 -05:00
  • b87ebf382f ARM: Add a function to decode VFP modified immediate constants. Gabe Black 2010-06-02 12:58:12 -05:00
  • 7eb4d02dd9 ARM: Add a function to decode SIMD modified immediate constants. Gabe Black 2010-06-02 12:58:12 -05:00
  • abda50173c ARM: Add fp operands to operands.isa. Gabe Black 2010-06-02 12:58:12 -05:00
  • 6365d29c21 ARM: Decode the VMRS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • fbf2ad5ae8 ARM: Update the set of FP related miscregs. Gabe Black 2010-06-02 12:58:11 -05:00
  • aade63a8fe ARM: Implement the VMRS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • a8b56b452c ARM: Decode the VMSR instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • 06008c54eb ARM: Implement the VMSR instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • 0ff71c7c34 ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers. Gabe Black 2010-06-02 12:58:11 -05:00
  • c9c4dfc09d ARM: Ignore attempts to disable coprocessors that aren't implemented anyway. Gabe Black 2010-06-02 12:58:11 -05:00
  • c3bf29bbea ARM: Implement the udiv instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • f3e65c2de2 ARM: Implement the sdiv instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • 5943f0fc84 ARM: Ignore writing a bad mode to CPSR with MSR. Gabe Black 2010-06-02 12:58:11 -05:00
  • ba33db8fd6 ARM: Decode the CPS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • 7861b084f6 ARM: Implement the CPS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • eb1447302d ARM: Decode the SRS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • bb6fea91da ARM: Implement the SRS instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • dbee6e0c54 ARM: Add a base class for SRS. Gabe Black 2010-06-02 12:58:11 -05:00
  • 239c9af90d ARM: Implement a badMode function that says whether a mode is legal. Gabe Black 2010-06-02 12:58:11 -05:00
  • a5ea52bb45 ARM: Allow flattening into any mode. Gabe Black 2010-06-02 12:58:11 -05:00
  • 698ee26c6b ARM: Decode TBB and TBH. Gabe Black 2010-06-02 12:58:11 -05:00
  • 6fa713a66c ARM: Decode the setend instruction. Gabe Black 2010-06-02 12:58:11 -05:00
  • 4683cd1655 ARM: Define the setend instruction. Gabe Black 2010-06-02 12:58:10 -05:00
  • fb23297914 ARM: Make a base class for instructions that use only an immediate. Gabe Black 2010-06-02 12:58:10 -05:00
  • 247acd93c4 ARM: Decode the arm version of ldrexd. Gabe Black 2010-06-02 12:58:10 -05:00
  • 3ad31f61c2 ARM: Decode the strex instructions. Gabe Black 2010-06-02 12:58:10 -05:00
  • 54ab07e636 ARM: Implement the strex instructions. Gabe Black 2010-06-02 12:58:10 -05:00
  • 524a8195e1 ARM: Set CPSR.E to SCTLR.EE on faults. Gabe Black 2010-06-02 12:58:10 -05:00
  • 683421e0c6 ARM: Warn about not implementing MPU translation, not panic about MMU. Gabe Black 2010-06-02 12:58:10 -05:00
  • 6fb5189c47 ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers. Gabe Black 2010-06-02 12:58:10 -05:00
  • 89b1dd5582 ARM: Allow access to the RGNR register. Gabe Black 2010-06-02 12:58:10 -05:00
  • c3381167c9 ARM: Make the MPUIR register report that 1 unified data region is supported. Gabe Black 2010-06-02 12:58:10 -05:00
  • 3aa8faf177 ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers. Gabe Black 2010-06-02 12:58:10 -05:00
  • faf6c727f6 ARM: Respect the E bit of the CPSR when doing loads and stores. Gabe Black 2010-06-02 12:58:10 -05:00
  • b6cb6f1874 ARM: Zero the micropc when vectoring to a fault. Gabe Black 2010-06-02 12:58:10 -05:00
  • 1d5233958a ARM: Implement the V7 version of alignment checking. Gabe Black 2010-06-02 12:58:10 -05:00
  • 7b397925af ARM: Decode the RFE instruction. Gabe Black 2010-06-02 12:58:10 -05:00
  • a2cb503ba6 ARM: Implement the RFE instruction. Gabe Black 2010-06-02 12:58:10 -05:00
  • ec4cd00b11 ARM: Add a base class for the RFE instruction. Gabe Black 2010-06-02 12:58:10 -05:00
  • 1ada9d4880 ARM: Make sure some undefined thumb32 instructions fault. Gabe Black 2010-06-02 12:58:10 -05:00
  • 3caa75d53a ARM: Squash the low order bits of the PC when performing a regular branch. Gabe Black 2010-06-02 12:58:10 -05:00
  • 36eeee0133 ARM: When changing the CPSR and branching, make sure the branch is second. Gabe Black 2010-06-02 12:58:09 -05:00
  • 68f2908a70 ARM: Ignore/warn when CSSELR or CCSIDR are accessed. Gabe Black 2010-06-02 12:58:09 -05:00
  • 741b243260 ARM: Ignore/warn access to the bpimva registers. Gabe Black 2010-06-02 12:58:09 -05:00
  • 8a7f60194e ARM: Ignore/warn on accesses to the dccmvac register. Gabe Black 2010-06-02 12:58:09 -05:00
  • 89133b15da ARM: Decode the enterx and leavex instructions. Gabe Black 2010-06-02 12:58:09 -05:00
  • 6a4ea7cca9 ARM: Implement the enterx and leavex instructions. Gabe Black 2010-06-02 12:58:09 -05:00
  • eb0823c4f2 ARM: Fix the implementation of BX to work in thumbEE mode. Gabe Black 2010-06-02 12:58:09 -05:00
  • bb0d390105 ARM: When an instruction is intentionally undefined, fault on it. Gabe Black 2010-06-02 12:58:09 -05:00
  • 61a5e71be7 ARM: Decode the thumb version of the ldrd and strd instructions. Gabe Black 2010-06-02 12:58:09 -05:00
  • 9d4a1bf2ba ARM: Explicitly keep track of the second destination for double loads/stores. Gabe Black 2010-06-02 12:58:09 -05:00
  • 28023f6f3d ARM: Decode the thumb32 load byte/memory hint instructions. Gabe Black 2010-06-02 12:58:09 -05:00
  • 7a9dcdf99f ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb. Gabe Black 2010-06-02 12:58:09 -05:00
  • a483d44d9f ARM: Ignore/warn on accesses to icimvau. Gabe Black 2010-06-02 12:58:09 -05:00
  • 630f309a77 ARM: Ignore/warn on iciallu. Gabe Black 2010-06-02 12:58:09 -05:00
  • d618121670 ARM: Ignore/warn on ICIALLUIS. Gabe Black 2010-06-02 12:58:09 -05:00
  • e658b6fed4 ARM: Add support for the clidr register. Gabe Black 2010-06-02 12:58:09 -05:00
  • 896c7617c4 ARM: Decode the unimplemented data barrier CP15 accesses. Gabe Black 2010-06-02 12:58:09 -05:00
  • af6b1667e9 ARM: Implement a stub of CPACR. Gabe Black 2010-06-02 12:58:09 -05:00
  • 660270746b ARM: Actually write the value of sctlr in ISA.clear(). Gabe Black 2010-06-02 12:58:08 -05:00
  • 6c9ab5d898 ARM: Replace the ARM decode of CP15 MCR and MRC instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 35f0c01fea ARM: Decode the unimplemented cp15 instruction barrier. Gabe Black 2010-06-02 12:58:08 -05:00
  • 7932b86298 ARM: Ignore accesses to DCCIMVAC. Gabe Black 2010-06-02 12:58:08 -05:00
  • 6ae4d34a12 ARM: Allow accesses to the software thread id registers. Gabe Black 2010-06-02 12:58:08 -05:00
  • 54850e4d23 ARM: Allow accesses to the contextidr register. Gabe Black 2010-06-02 12:58:08 -05:00
  • 221e0ac523 ARM: Warn about and ignore accesses to DCCISW. Gabe Black 2010-06-02 12:58:08 -05:00
  • 8c1be04af6 ARM: Decode the thumb versions of the mcr and mrc instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 625a43e7c7 ARM: Implement the mrc and mcr instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 6c1b10043f ARM: Rename the RevOp base class to something more generic. Gabe Black 2010-06-02 12:58:08 -05:00
  • f9d1bba22a ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs. Gabe Black 2010-06-02 12:58:08 -05:00
  • 6aa229386d ARM: Implement a function to decode CP15 registers to MiscReg indices. Gabe Black 2010-06-02 12:58:08 -05:00
  • 7ff24c8777 ARM: Decode the bfi and bfc instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • a37b6b6bce ARM: Implement the bfc and bfi instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 5a63887617 ARM: Decode the ubfx and sbfx instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 2e717558e2 ARM: Decode miscellaneous arm mode media instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • 09cc401848 ARM: Implement the ubfx and sbfx instructions. Gabe Black 2010-06-02 12:58:08 -05:00
  • b1158e4938 ARM: Add a register, immediate, immediate to register base for [su]bfx. Gabe Black 2010-06-02 12:58:08 -05:00
  • 504ac6518b ARM: Decode the clz instruction. Gabe Black 2010-06-02 12:58:08 -05:00
  • 2c94bf7f30 ARM: Implement the clz instruction. Gabe Black 2010-06-02 12:58:08 -05:00
  • 00320a53ab ARM: Decode the rbit instruction. Gabe Black 2010-06-02 12:58:07 -05:00
  • 5cc1bb6842 ARM: Implement the rbit instruction. Gabe Black 2010-06-02 12:58:07 -05:00
  • 566b2ff20c ARM: Decode the nop instruction. Gabe Black 2010-06-02 12:58:07 -05:00
  • b9cfe9a3db ARM: Implement nop. Gabe Black 2010-06-02 12:58:07 -05:00
  • a2d8dcebba ARM: Decode the ldrex instruction. Gabe Black 2010-06-02 12:58:07 -05:00
  • 952253483b ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. Gabe Black 2010-06-02 12:58:07 -05:00