ARM: Implement a function to decode CP15 registers to MiscReg indices.
This commit is contained in:
Gabe Black
@@ -54,6 +54,7 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/misc.cc')
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Source('insts/pred_inst.cc')
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Source('insts/static_inst.cc')
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Source('miscregs.cc')
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Source('nativetrace.cc')
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Source('pagetable.cc')
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Source('tlb.cc')
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@@ -152,6 +152,11 @@ namespace ArmISA
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cpsr.t = 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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return readMiscRegNoEffect(misc_reg);
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}
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@@ -205,6 +210,11 @@ namespace ArmISA
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tc->setNextPC(npc);
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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}
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return setMiscRegNoEffect(misc_reg, val);
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}
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323
src/arch/arm/miscregs.cc
Normal file
323
src/arch/arm/miscregs.cc
Normal file
@@ -0,0 +1,323 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/miscregs.hh"
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namespace ArmISA
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{
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MiscRegIndex
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decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
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{
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switch (crn) {
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case 0:
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switch (opc1) {
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case 0:
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switch (crm) {
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case 0:
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switch (opc2) {
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case 1:
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return MISCREG_CTR;
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case 2:
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return MISCREG_TCMTR;
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case 4:
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return MISCREG_MPUIR;
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case 5:
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return MISCREG_MPIDR;
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default:
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return MISCREG_MIDR;
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}
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break;
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case 1:
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switch (opc2) {
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case 0:
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return MISCREG_ID_PFR0;
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case 1:
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return MISCREG_ID_PFR1;
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case 2:
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return MISCREG_ID_DFR0;
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case 3:
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return MISCREG_ID_AFR0;
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case 4:
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return MISCREG_ID_MMFR0;
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case 5:
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return MISCREG_ID_MMFR1;
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case 6:
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return MISCREG_ID_MMFR2;
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case 7:
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return MISCREG_ID_MMFR3;
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}
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break;
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case 2:
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switch (opc2) {
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case 0:
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return MISCREG_ID_ISAR0;
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case 1:
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return MISCREG_ID_ISAR1;
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case 2:
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return MISCREG_ID_ISAR2;
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case 3:
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return MISCREG_ID_ISAR3;
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case 4:
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return MISCREG_ID_ISAR4;
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case 5:
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return MISCREG_ID_ISAR5;
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case 6:
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case 7:
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return MISCREG_RAZ; // read as zero
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}
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break;
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default:
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return MISCREG_RAZ; // read as zero
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}
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break;
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case 1:
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if (crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_CCSIDR;
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case 1:
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return MISCREG_CLIDR;
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case 7:
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return MISCREG_AIDR;
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}
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}
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break;
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case 2:
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if (crm == 0 && opc2 == 0) {
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return MISCREG_CSSELR;
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}
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break;
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}
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break;
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case 1:
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if (opc1 == 0 && crm == 0) {
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switch (opc2) {
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case 0:
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return MISCREG_SCTLR;
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case 1:
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return MISCREG_ACTLR;
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case 0x2:
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return MISCREG_CPACR;
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}
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}
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break;
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case 5:
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if (opc1 == 0) {
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if (crm == 0) {
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if (opc2 == 0) {
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return MISCREG_DFSR;
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} else if (opc2 == 1) {
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return MISCREG_IFSR;
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}
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} else if (crm == 1) {
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if (opc2 == 0) {
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return MISCREG_ADFSR;
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} else if (opc2 == 1) {
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return MISCREG_AIFSR;
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}
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}
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}
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break;
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case 6:
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if (opc1 == 0) {
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switch (crm) {
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case 0:
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switch (opc2) {
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case 0:
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return MISCREG_DFAR;
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case 2:
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return MISCREG_IFAR;
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}
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break;
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case 1:
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switch (opc2) {
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case 0:
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return MISCREG_DRBAR;
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case 1:
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return MISCREG_IRBAR;
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case 2:
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return MISCREG_DRSR;
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case 3:
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return MISCREG_IRSR;
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case 4:
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return MISCREG_DRACR;
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case 5:
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return MISCREG_IRACR;
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}
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break;
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case 2:
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if (opc2 == 0) {
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return MISCREG_RGNR;
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}
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}
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}
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break;
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case 7:
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if (opc1 == 0) {
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switch (crm) {
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case 0:
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if (opc2 == 4) {
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return MISCREG_NOP;
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}
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break;
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case 1:
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switch (opc2) {
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case 0:
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return MISCREG_ICIALLUIS;
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case 6:
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return MISCREG_BPIALLIS;
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}
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break;
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case 5:
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switch (opc2) {
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case 0:
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return MISCREG_ICIALLU;
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case 1:
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return MISCREG_ICIMVAU;
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case 4:
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return MISCREG_CP15ISB;
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case 6:
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return MISCREG_BPIALL;
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case 7:
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return MISCREG_BPIMVA;
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}
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break;
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case 6:
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if (opc2 == 1) {
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return MISCREG_DCIMVAC;
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} else if (opc2 == 2) {
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return MISCREG_DCISW;
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}
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break;
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case 10:
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switch (opc2) {
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case 1:
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return MISCREG_DCCMVAC;
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case 2:
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return MISCREG_MCCSW;
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case 4:
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return MISCREG_CP15DSB;
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case 5:
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return MISCREG_CP15DMB;
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}
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break;
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case 11:
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if (opc2 == 1) {
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return MISCREG_DCCMVAU;
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}
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break;
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case 13:
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if (opc2 == 1) {
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return MISCREG_NOP;
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}
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break;
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case 14:
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if (opc2 == 1) {
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return MISCREG_DCCIMVAC;
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} else if (opc2 == 2) {
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return MISCREG_DCCISW;
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}
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break;
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}
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}
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break;
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case 9:
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if (opc1 >= 0 && opc1 <= 7) {
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switch (crm) {
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case 0:
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case 1:
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case 2:
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case 5:
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case 6:
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case 7:
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case 8:
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//Reserved for Branch Predictor, Cache and TCM operations
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case 12:
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case 13:
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case 14:
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case 15:
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// Reserved for Performance monitors
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break;
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}
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}
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break;
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case 11:
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if (opc1 >= 0 && opc1 <=7) {
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switch (crm) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case 8:
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case 15:
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// Reserved for DMA operations for TCM access
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break;
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}
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}
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break;
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case 13:
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if (opc1 == 0) {
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if (crm == 0) {
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switch (crm) {
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case 1:
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return MISCREG_CONTEXTIDR;
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case 2:
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return MISCREG_TPIDRURW;
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case 3:
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return MISCREG_TPIDRURO;
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case 4:
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return MISCREG_TPIDRPRW;
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}
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}
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}
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break;
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case 15:
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// Implementation defined
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break;
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}
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// Unrecognized register
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return NUM_MISCREGS;
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}
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};
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@@ -78,13 +78,98 @@ namespace ArmISA
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MISCREG_FPSID,
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MISCREG_FPSCR,
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MISCREG_FPEXC,
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MISCREG_SCTLR,
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// CP15 registers
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MISCREG_CP15_START,
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MISCREG_SCTLR = MISCREG_CP15_START,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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MISCREG_MPUIR,
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MISCREG_MPIDR,
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MISCREG_MIDR,
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MISCREG_ID_PFR0,
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MISCREG_ID_PFR1,
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MISCREG_ID_DFR0,
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MISCREG_ID_AFR0,
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MISCREG_ID_MMFR0,
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MISCREG_ID_MMFR1,
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MISCREG_ID_MMFR2,
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MISCREG_ID_MMFR3,
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MISCREG_ID_ISAR0,
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MISCREG_ID_ISAR1,
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MISCREG_ID_ISAR2,
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MISCREG_ID_ISAR3,
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MISCREG_ID_ISAR4,
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MISCREG_ID_ISAR5,
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MISCREG_CCSIDR,
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MISCREG_CLIDR,
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MISCREG_AIDR,
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MISCREG_CSSELR,
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MISCREG_ACTLR,
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MISCREG_CPACR,
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MISCREG_DFSR,
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MISCREG_IFSR,
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MISCREG_ADFSR,
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MISCREG_AIFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_DRBAR,
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MISCREG_IRBAR,
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MISCREG_DRSR,
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MISCREG_IRSR,
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MISCREG_DRACR,
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MISCREG_IRACR,
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MISCREG_RGNR,
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MISCREG_ICIALLUIS,
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MISCREG_BPIALLIS,
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MISCREG_ICIALLU,
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MISCREG_ICIMVAU,
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MISCREG_CP15ISB,
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MISCREG_BPIALL,
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MISCREG_BPIMVA,
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MISCREG_DCIMVAC,
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MISCREG_DCISW,
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MISCREG_DCCMVAC,
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MISCREG_MCCSW,
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MISCREG_CP15DSB,
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MISCREG_CP15DMB,
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MISCREG_DCCMVAU,
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MISCREG_DCCIMVAC,
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MISCREG_DCCISW,
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MISCREG_CONTEXTIDR,
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MISCREG_TPIDRURW,
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MISCREG_TPIDRURO,
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MISCREG_TPIDRPRW,
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MISCREG_CP15_END,
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// Dummy indices
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MISCREG_NOP = MISCREG_CP15_END,
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MISCREG_RAZ,
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NUM_MISCREGS
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};
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MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
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unsigned crm, unsigned opc2);
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const char * const miscRegName[NUM_MISCREGS] = {
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
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"spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
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"spsr_mon", "spsr_und", "spsr_abt",
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"fpsr", "fpsid", "fpscr", "fpexc",
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"sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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"ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
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"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
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"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
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"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
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"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
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"cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
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"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
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"nop", "raz"
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};
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BitUnion32(CPSR)
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