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ARM: Add fp operands to operands.isa.

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Gabe Black
2010-06-02 12:58:12 -05:00
parent 6365d29c21
commit abda50173c
1 changed files with 20 additions and 0 deletions
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20
src/arch/arm/isa/operands.isa
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@@ -91,10 +91,20 @@ def operands {{
#Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
@@ -109,9 +119,19 @@ def operands {{
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,