ARM: Ignore/warn on accesses to the dccmvac register.

src/arch/arm/isa/formats/misc.isa

@@ -100,7 +100,10 @@ def format McrMrc15() {{
                     isRead ? "mrc dccisw" : "mcr dcisw", machInst);
           case MISCREG_DCCIMVAC:
             return new WarnUnimplemented(
-                    isRead ? "mrc dccimvac" : "mcr dcimvac", machInst);
+                    isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
+          case MISCREG_DCCMVAC:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
           case MISCREG_CP15ISB:
             return new WarnUnimplemented(
                     isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);

src/arch/arm/miscregs.hh

@@ -84,6 +84,7 @@ namespace ArmISA
         MISCREG_SCTLR = MISCREG_CP15_START,
         MISCREG_DCCISW,
         MISCREG_DCCIMVAC,
+        MISCREG_DCCMVAC,
         MISCREG_CONTEXTIDR,
         MISCREG_TPIDRURW,
         MISCREG_TPIDRURO,
@@ -138,7 +139,6 @@ namespace ArmISA
         MISCREG_BPIMVA,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
-        MISCREG_DCCMVAC,
         MISCREG_MCCSW,
         MISCREG_DCCMVAU,
 
@@ -158,7 +158,7 @@ namespace ArmISA
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
         "fpsr", "fpsid", "fpscr", "fpexc",
-        "sctlr", "dccisw", "dccimvac",
+        "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
         "icialluis", "iciallu", "icimvau",
@@ -170,7 +170,7 @@ namespace ArmISA
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
         "rgnr", "bpiallis",
-        "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
+        "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nop", "raz"
     };