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ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.

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This commit is contained in:
Gabe Black
2010-06-02 12:58:07 -05:00
parent f7f75ad053
commit 952253483b
4 changed files with 65 additions and 43 deletions
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1
src/arch/arm/isa/bitfields.isa
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@@ -148,6 +148,7 @@ def bitfield HTOPCODE_8_6 htopcode8_6;
def bitfield HTOPCODE_8_5 htopcode8_5;
def bitfield HTOPCODE_7 htopcode7;
def bitfield HTOPCODE_7_5 htopcode7_5;
def bitfield HTOPCODE_6 htopcode6;
def bitfield HTOPCODE_6_5 htopcode6_5;
def bitfield HTOPCODE_5_4 htopcode5_4;
def bitfield HTOPCODE_4 htopcode4;

52
src/arch/arm/isa/decoder/thumb.isa
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@@ -68,50 +68,16 @@
// 32 bit thumb instructions.
1: decode HTOPCODE_12_11 {
0x1: decode HTOPCODE_10_9 {
0x0: decode HTOPCODE_8_6 {
0x0, 0x6: decode HTOPCODE_4 {
0x0: WarnUnimpl::srs();
0x1: WarnUnimpl::rfe();
}
0x1: decode HTOPCODE_5_4 {
0x0: WarnUnimpl::strex();
0x1: WarnUnimpl::ldrex();
0x2: WarnUnimpl::strd(); // immediate
0x3: decode HTRN {
0xf: WarnUnimpl::ldrd(); // literal
default: WarnUnimpl::ldrd(); // immediate
}
}
// This uses the same encoding as regular ARM.
0x2: ArmMacroMem::armMacroMem();
0x3: decode HTOPCODE_5_4 {
0x0: decode LTOPCODE_7_4 {
0x4: WarnUnimpl::strexb();
0x5: WarnUnimpl::strexh();
0x7: WarnUnimpl::strexd();
}
0x1: decode LTOPCODE_7_4 {
0x0: WarnUnimpl::tbb();
0x1: WarnUnimpl::tbh();
0x4: WarnUnimpl::ldrexb();
0x5: WarnUnimpl::ldrexh();
0x7: WarnUnimpl::ldrexd();
}
0x2: WarnUnimpl::strd(); // immediate
0x3: decode HTRN {
0xf: WarnUnimpl::ldrd(); // literal
default: WarnUnimpl::ldrd(); // immediate
}
}
// This uses the same encoding as regular ARM.
0x4: ArmMacroMem::armMacroMem();
0x5, 0x7: decode HTOPCODE_4 {
0x0: WarnUnimpl::strd(); // immediate
0x1: decode HTRN {
0xf: WarnUnimpl::ldrd(); // literal
default: WarnUnimpl::ldrd(); // immediate
}
0x0: decode HTOPCODE_6 {
0x0: decode HTOPCODE_8_7 {
0x0, 0x3: decode HTOPCODE_4 {
0x0: WarnUnimpl::srs();
0x1: WarnUnimpl::rfe();
}
// This uses the same encoding as regular ARM.
default: ArmMacroMem::armMacroMem();
}
0x1: Thumb32LdrStrDExTbh::thumb32LdrStrDExTbh();
}
0x1: Thumb32DataProcShiftReg::thumb32DataProcShiftReg();
default: decode HTOPCODE_9_8 {

54
src/arch/arm/isa/formats/mem.isa
View File

@@ -235,6 +235,60 @@ def format ArmSyncMem() {{
'''
}};
def format Thumb32LdrStrDExTbh() {{
decode_block = '''
{
const uint32_t op1 = bits(machInst, 24, 23);
const uint32_t op2 = bits(machInst, 21, 20);
const uint32_t op3 = bits(machInst, 7, 4);
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
if (op1 == 0) {
if (op2 == 0) {
return new WarnUnimplemented("strex", machInst);
} else {
return new WarnUnimplemented("ldrex", machInst);
}
} else {
if (op2 == 0) {
switch (op3) {
case 0x4:
return new WarnUnimplemented("strexb", machInst);
case 0x5:
return new WarnUnimplemented("strexh", machInst);
case 0x7:
return new WarnUnimplemented("strexd", machInst);
default:
return new Unknown(machInst);
}
} else {
switch (op3) {
case 0x0:
return new WarnUnimplemented("tbb", machInst);
case 0x1:
return new WarnUnimplemented("tbh", machInst);
case 0x4:
return new WarnUnimplemented("ldrexb", machInst);
case 0x5:
return new WarnUnimplemented("ldrexh", machInst);
case 0x7:
return new WarnUnimplemented("ldrexd", machInst);
default:
return new Unknown(machInst);
}
}
}
} else {
if (bits(op2, 0) == 0) {
return new WarnUnimplemented("strd", machInst);
} else {
return new WarnUnimplemented("ldrd", machInst);
}
}
}
'''
}};
def format Thumb32LoadWord() {{
decode = '''
{

1
src/arch/arm/types.hh
View File

@@ -159,6 +159,7 @@ namespace ArmISA
Bitfield<24, 21> htopcode8_5;
Bitfield<23> htopcode7;
Bitfield<23, 21> htopcode7_5;
Bitfield<22> htopcode6;
Bitfield<22, 21> htopcode6_5;
Bitfield<21, 20> htopcode5_4;
Bitfield<20> htopcode4;