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  • bf903ec9a1 ARM: Get rid of the unused Jump format. Gabe Black 2010-06-02 12:58:02 -05:00
  • 36ca0658a4 ARM: Get rid of obsoleted predicated inst formats, etc. Gabe Black 2010-06-02 12:58:02 -05:00
  • 7939b48265 ARM: Implement disassembly for the new data processing classes. Gabe Black 2010-06-02 12:58:02 -05:00
  • b66e3aec43 ARM: Hook the external data processing instructions into the Thumb decoder. Gabe Black 2010-06-02 12:58:02 -05:00
  • beb759912b ARM: Move the modified_imm function from all ARM instructions to just data processing ones. Gabe Black 2010-06-02 12:58:02 -05:00
  • 8136cb3605 ARM: Hook the new external data processing instructions to the ARM decoder. Gabe Black 2010-06-02 12:58:02 -05:00
  • bf45d44cbe ARM: Implement data processing instructions external to the decoder. Gabe Black 2010-06-02 12:58:02 -05:00
  • c02f9cdddf ARM: Add new base classes for data processing instructions. Gabe Black 2010-06-02 12:58:02 -05:00
  • 1e7b317a98 ARM: Hook up 32 bit thumb load/store multiple. Gabe Black 2010-06-02 12:58:02 -05:00
  • 64d6b6ebfd ARM: Hook up 16 bit thumb load/store multiple. Gabe Black 2010-06-02 12:58:02 -05:00
  • 51bde086d5 ARM: Reimplement load/store multiple external to the decoder. Gabe Black 2010-06-02 12:58:02 -05:00
  • 93a3714816 ARM: Move the templates for predicated instructions into a separate file. This allows the templates to all be available at the same time before any of the formats, etc. This breaks an artificial circular dependence. Gabe Black 2010-06-02 12:58:01 -05:00
  • 04300e33d4 ARM: Remove the special naming for the new memory instructions. These are the only memory instructions now. Gabe Black 2010-06-02 12:58:01 -05:00
  • deb6e8f805 ARM: Eliminate the old memory formats which are no longer used. Gabe Black 2010-06-02 12:58:01 -05:00
  • 1905024766 ARM: Eliminate decoding for the very deprecated FPA instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 55465844dc ARM: Make the addressing mode 3 loads/stores use the externally defined instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. Gabe Black 2010-06-02 12:58:01 -05:00
  • 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional. Before, because 16 bit thumb instructions didn't set the upper 16 bits of the ExtMachInst, that field would be interpretted as "equals". Gabe Black 2010-06-02 12:58:01 -05:00
  • a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 462cf6f49b ARM: Make single stores decode to the new external store instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions. This isn't technically correct since the .w should only be added if there are 32 and 16 bit encodings, but always having it always is better than never having it. Gabe Black 2010-06-02 12:58:01 -05:00
  • fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 3b93015304 ARM: Define the store instructions from outside the decoder. Gabe Black 2010-06-02 12:58:01 -05:00
  • 81fdced83f ARM: Define the load instructions from outside the decoder. Gabe Black 2010-06-02 12:58:01 -05:00
  • 321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder. Gabe Black 2010-06-02 12:58:01 -05:00
  • 4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 386424ccb5 ARM: Implement the 32 bit thumb load word instructions. Gabe Black 2010-06-02 12:58:01 -05:00
  • 292b8a3c91 ARM: Add an operand for accessing the current PC. Gabe Black 2010-06-02 12:58:00 -05:00
  • 003346077f ARM: Flesh out 32 bit thumb load word decoding. Gabe Black 2010-06-02 12:58:00 -05:00
  • 0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. Gabe Black 2010-06-02 12:58:00 -05:00
  • bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. Gabe Black 2010-06-02 12:58:00 -05:00
  • af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. Gabe Black 2010-06-02 12:58:00 -05:00
  • bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. Gabe Black 2010-06-02 12:58:00 -05:00
  • 0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. Gabe Black 2010-06-02 12:58:00 -05:00
  • cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. Gabe Black 2010-06-02 12:58:00 -05:00
  • 659f8d021f ARM: Add bitfields for 32 bit thumb. Gabe Black 2010-06-02 12:58:00 -05:00
  • bc6ae010c9 ARM: Decode VFP instructions. Gabe Black 2010-06-02 12:58:00 -05:00
  • 7b8525287d ARM: Stub out the 16 bit thumb decoder. Gabe Black 2010-06-02 12:58:00 -05:00
  • aaa619ea23 ARM: Add thumb bitfields to the ExtMachInst and the isa definition. Gabe Black 2010-06-02 12:58:00 -05:00
  • a1838f2c79 ARM: Make the decoder handle thumb instructions separately. Gabe Black 2010-06-02 12:58:00 -05:00
  • 0dffd8ce79 ARM: Add a thumb bit bitfield. Gabe Black 2010-06-02 12:58:00 -05:00
  • 96be7e16c1 ARM: Make the predecoder handle Thumb instructions. Gabe Black 2010-06-02 12:58:00 -05:00
  • f49cdb4f5d ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. Gabe Black 2010-06-02 12:58:00 -05:00
  • 330d9d4dbc ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. Gabe Black 2010-06-02 12:58:00 -05:00
  • a59d219989 ARM: Add a bit to the ExtMachInst to select thumb mode. Gabe Black 2010-06-02 12:58:00 -05:00
  • 4ddeceba96 ARM: Allow ARM processes to start in Thumb mode. Gabe Black 2010-06-02 12:58:00 -05:00
  • 3951afd2fa ARM: Detect thumb mode elf images. Gabe Black 2010-06-02 12:58:00 -05:00
  • ebb273bb7b ARM: Add a new base class for instructions that can do an interworking branch. Gabe Black 2010-06-02 12:57:59 -05:00
  • 9ef82c0bc4 ARM: Track the current ISA mode using the PC. Gabe Black 2010-06-02 12:57:59 -05:00
  • 1c0d9806e5 ARM: Fix custom writer/reader code for non indexed operands. Gabe Black 2010-06-02 12:57:59 -05:00
  • 4b87bc887a ARM: Remove IsControl from operands that don't imply control transfers. Gabe Black 2010-06-02 12:57:59 -05:00
  • 322f345b51 ARM: Adjust some copyrights Ali Saidi 2010-06-02 12:57:59 -05:00
  • c1aabe8172 style: clean up ruby's Set class Nathan Binkert 2010-06-01 11:38:56 -07:00
  • bb589d463b x86: put back code that I accidentally deleted Nathan Binkert 2010-05-25 20:15:44 -07:00
  • 13d64906c2 copyright: Change HP copyright on x86 code to be more friendly Nathan Binkert 2010-05-23 22:44:15 -07:00
  • a990335b32 BPRED: Update one missing regression Ali Saidi 2010-05-19 00:36:05 -04:00
  • c5c559b6ab SPARC: Implement the version of movcc that uses the fp condition codes. Gabe Black 2010-05-14 14:22:51 -07:00
  • 72071690e7 Automated merge with ssh://m5sim.org//repo/m5 Ali Saidi 2010-05-13 23:48:06 -04:00
  • e63c73b45d BPRED: Update regressions for tournament predictor fix. Ali Saidi 2010-05-13 23:45:59 -04:00
  • fc746c2268 BPRED: Fixed the treshold-bug in the tournament predictor. Maximilien Breughe 2010-05-13 23:45:57 -04:00
  • c4497dbf03 X86: Make the cvti2f microop sign extend its integer source correctly. Gabe Black 2010-05-12 00:51:35 -07:00
  • cc76842f83 X86: Actual change that fixes div. How did that happen? Gabe Black 2010-05-12 00:49:12 -07:00
  • 776e8d5c8e X86: The logic that handled the recently fixed corner case for div wasn't quite right. Gabe Black 2010-05-12 00:37:29 -07:00
  • d984593855 Merge. Gabe Black 2010-05-06 13:41:33 -07:00
  • 81e68287bb X86: Update the stats for the new aux vectors in the ruby regression. I forgot to turn on ruby when updating the stats before. Gabe Black 2010-05-06 13:41:08 -07:00
  • c4057a13f1 macos: MacOS has deprecated getdirentries, so just disable the code. Hopefully it isn't used much Nathan Binkert 2010-05-06 08:42:21 -07:00
  • f07ee128cc compile: don't #include unnecessary stuff Time from base/time.hh has a name clash with Time from Ruby's TypeDefines.hh. Eventually Ruby's Time should go away, so instead of fixing this properly just try to avoid the clash. Nathan Binkert 2010-05-06 08:42:18 -07:00
  • 8b0c83008e X86: Update stats for the updated auxilliary vectors. Gabe Black 2010-05-03 00:45:01 -07:00
  • 2ee7a89209 X86: Update the base aux vector X86 processes install. Gabe Black 2010-05-03 00:44:08 -07:00
  • 7524fdda6a X86: Sometimes CPUID depends on ecx, so pass that in. Gabe Black 2010-05-02 00:40:17 -07:00
  • d75ad847b3 Statetrace: Fix compile problems with the AMD64 version of statetrace. Gabe Black 2010-05-02 00:39:46 -07:00
  • 51a3d65e25 X86: Finally fix a division corner case. Gabe Black 2010-05-02 00:39:29 -07:00
  • 90820ddf02 config: fix assertion for x86 in FSConfig.py Nathan Binkert 2010-04-18 21:33:59 -07:00
  • 82fb350f9a stats: make simTicks and simFreq accessible from stats.hh Nathan Binkert 2010-04-18 13:23:25 -07:00
  • 50bf3895b0 callback: Make helper functions that create callback objects for you clean up callback stuff a little bit while we're at it. Nathan Binkert 2010-04-18 13:23:25 -07:00
  • 12fc22571c event: Allow EventWrapper to take an object reference Nathan Binkert 2010-04-18 13:23:24 -07:00
  • 4225a68a95 scons: don't maintain files in sorted order This causes builds to happen in sorted order rather than in declaration order. This gets annoying when you make a global change and then you notice that the files that are being compiled are jumping around the directory hierarchy. Nathan Binkert 2010-04-15 16:25:14 -07:00
  • e99828b06a tick: rename Clock namespace to SimClock Nathan Binkert 2010-04-15 16:24:12 -07:00
  • f7e6f19ada eventq: move EventQueue constructor to cc file Also make copy constructor and assignment operator private. Nathan Binkert 2010-04-15 16:24:10 -07:00
  • c90ee27283 inorder: update regressions for fwd-ing patch Korey Sewell 2010-04-11 00:21:49 -04:00
  • b49511ae48 inorder: timing for inst forwarding when insts execute, they mark the time they finish to be used for subsequent isnts they may need forwarding of data. However, the regdepmap was using the wrong value to index into the destination operands of the instruction to be forwarded. Thus, in some cases, we are checking to see if the 3rd destination register for an instruction is executed at a certain time, when there is only 1 dest. register valid. Thus, we get a bad, uninitialized time value that will stall forwarding causing performance loss but still the correct execution. Korey Sewell 2010-04-10 23:31:36 -04:00
  • d71f9712b3 eventq: allow an implicit cast from an EventManager to an EventQueue * Nathan Binkert 2010-04-02 15:28:22 -07:00
  • f32674d9bc eventq: Clean up some flags - Make the initialized flag always available, not just in debug mode. - Make the Initialized flag actually use several bits so it is very unlikely that something that's uninitialized accidentally looks initialized. - Add an initialized() function that tells you if the current event is indeed initialized. - Clear the flags on delete so it can't be accidentally thought of as initialized. - Fix getFlags assert statement. "How did this ever work?" Nathan Binkert 2010-04-02 15:28:22 -07:00
  • 2ee3edba8e eventq: Make priorities just an integer instead of an enum. Symbolic names should still be used, but this makes it easier to do things like: Event::Priority MyObject_Pri = Event::Default_Pri + 1 Nathan Binkert 2010-04-02 15:28:21 -07:00
  • 01dffaa32f refcnt: no default copy contructor or copy operator We shouldn't allow these because the default versions will copy the reference count which is definitely not what we want. Nathan Binkert 2010-04-02 11:20:32 -07:00
  • 141f61d83a ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base Nathan Binkert 2010-04-02 11:20:32 -07:00
  • f1c3f3044b ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. Nathan Binkert 2010-04-02 11:20:32 -07:00
  • be10204729 style: another ruby style pass Nathan Binkert 2010-03-31 16:56:45 -07:00
  • 60ae1d2b10 style: cleanup the Ruby Tester Nathan Binkert 2010-03-29 20:39:02 -04:00
  • 1c98bc5a56 m5: merge inorder updates Korey Sewell 2010-03-27 02:23:00 -04:00
  • 941399728f inorder: update twolf/vortex regressions Korey Sewell 2010-03-27 02:21:22 -04:00
  • ac316d45e8 inorder: write-hints bug fix make sure to only read 1 src reg. for write-hint and any other similar 'store' instruction. Reading the source reg when its not necessary can cause the simulator to read from uninitialized values Korey Sewell 2010-03-27 01:40:05 -04:00
  • 6b293c73fd CPU: Added comments to address translation classes. Timothy M. Jones 2010-03-25 12:43:52 +00:00
  • a2652a048a ruby: continue style pass Nathan Binkert 2010-03-23 22:49:43 -07:00
  • d2eb589675 regress: add some new options add -n/--no-exec which doesn't execute scons, but just prints the command line add -j0 which tries to calculate how many cpus you have add -D/--build-dir to specify a build directory other than ./build Nathan Binkert 2010-03-23 16:31:47 -07:00
  • f066bfc2f5 cpu: get rid of uncached access "events" These recordEvent() calls could cause crashes since they access the req pointer after it's potentially been deleted during a failed translation call. (Similar problem to the traceData bug fixed in the previous cset.) Steve Reinhardt 2010-03-23 08:50:59 -07:00
  • 4d77ea7a57 cpu: fix exec tracing memory corruption bug Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. Steve Reinhardt 2010-03-23 08:50:57 -07:00