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ARM: Remove the special naming for the new memory instructions.

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These are the only memory instructions now.
This commit is contained in:
Gabe Black
2010-06-02 12:58:01 -05:00
parent deb6e8f805
commit 04300e33d4
5 changed files with 93 additions and 93 deletions
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2
src/arch/arm/insts/mem.cc
View File

@@ -47,7 +47,7 @@ namespace ArmISA
{
void
MemoryNew::printInst(std::ostream &os, AddrMode addrMode) const
Memory::printInst(std::ostream &os, AddrMode addrMode) const
{
printMnemonic(os);
printReg(os, dest);

142
src/arch/arm/insts/mem.hh
View File

@@ -47,7 +47,7 @@
namespace ArmISA
{
class MemoryNew : public PredOp
class Memory : public PredOp
{
public:
enum AddrMode {
@@ -62,8 +62,8 @@ class MemoryNew : public PredOp
IntRegIndex base;
bool add;
MemoryNew(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add)
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add)
: PredOp(mnem, _machInst, __opClass),
dest(_dest), base(_base), add(_add)
{}
@@ -76,14 +76,14 @@ class MemoryNew : public PredOp
};
// The address is a base register plus an immediate.
class MemoryNewImm : public MemoryNew
class MemoryImm : public Memory
{
protected:
int32_t imm;
MemoryNewImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
: MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
: Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
{}
void
@@ -97,18 +97,18 @@ class MemoryNewImm : public MemoryNew
};
// The address is a shifted register plus an immediate
class MemoryNewReg : public MemoryNew
class MemoryReg : public Memory
{
protected:
int32_t shiftAmt;
ArmShiftType shiftType;
IntRegIndex index;
MemoryNewReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add),
MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: Memory(mnem, _machInst, __opClass, _dest, _base, _add),
shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
{}
@@ -150,16 +150,70 @@ class MemoryNewReg : public MemoryNew
};
template<class Base>
class MemoryNewOffset : public Base
class MemoryOffset : public Base
{
protected:
MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
MemoryOffset(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryOffset(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
this->printInst(ss, Memory::AddrMd_Offset);
return ss.str();
}
};
template<class Base>
class MemoryPreIndex : public Base
{
protected:
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
this->printInst(ss, Memory::AddrMd_PreIndex);
return ss.str();
}
};
template<class Base>
class MemoryPostIndex : public Base
{
protected:
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
@@ -171,61 +225,7 @@ class MemoryNewOffset : public Base
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
this->printInst(ss, MemoryNew::AddrMd_Offset);
return ss.str();
}
};
template<class Base>
class MemoryNewPreIndex : public Base
{
protected:
MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
this->printInst(ss, MemoryNew::AddrMd_PreIndex);
return ss.str();
}
};
template<class Base>
class MemoryNewPostIndex : public Base
{
protected:
MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
IntRegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
this->printInst(ss, MemoryNew::AddrMd_PostIndex);
this->printInst(ss, Memory::AddrMd_PostIndex);
return ss.str();
}
};

16
src/arch/arm/isa/insts/ldr.isa
View File

@@ -64,10 +64,10 @@ let {{
(newHeader,
newDecoder,
newExec) = newLoadStoreBase(name, Name, imm,
eaCode, accCode,
memFlags, instFlags,
base, execTemplateBase = 'Load')
newExec) = loadStoreBase(name, Name, imm,
eaCode, accCode,
memFlags, instFlags,
base, execTemplateBase = 'Load')
header_output += newHeader
decoder_output += newDecoder
@@ -93,7 +93,7 @@ let {{
accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewImm", post, writeback)
base = buildMemBase("MemoryImm", post, writeback)
emitLoad(name, Name, True, eaCode, accCode, [], [], base)
@@ -118,7 +118,7 @@ let {{
accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewReg", post, writeback)
base = buildMemBase("MemoryReg", post, writeback)
emitLoad(name, Name, False, eaCode, accCode, [], [], base)
@@ -143,7 +143,7 @@ let {{
'''
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewImm", post, writeback)
base = buildMemBase("MemoryImm", post, writeback)
emitLoad(name, Name, True, eaCode, accCode, [], [], base)
@@ -169,7 +169,7 @@ let {{
'''
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewReg", post, writeback)
base = buildMemBase("MemoryReg", post, writeback)
emitLoad(name, Name, False, eaCode, accCode, [], [], base)

10
src/arch/arm/isa/insts/mem.isa
View File

@@ -38,8 +38,8 @@
// Authors: Gabe Black
let {{
def newLoadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
instFlags, base = 'MemoryNew', execTemplateBase = ''):
def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
instFlags, base = 'Memory', execTemplateBase = ''):
# Make sure flags are in lists (convert to lists if not).
memFlags = makeList(memFlags)
instFlags = makeList(instFlags)
@@ -131,11 +131,11 @@ let {{
def buildMemBase(base, post, writeback):
if post and writeback:
base = "MemoryNewPostIndex<%s>" % base
base = "MemoryPostIndex<%s>" % base
elif not post and writeback:
base = "MemoryNewPreIndex<%s>" % base
base = "MemoryPreIndex<%s>" % base
elif not post and not writeback:
base = "MemoryNewOffset<%s>" % base
base = "MemoryOffset<%s>" % base
else:
raise Exception, "Illegal combination of post and writeback"
return base

16
src/arch/arm/isa/insts/str.isa
View File

@@ -66,10 +66,10 @@ let {{
(newHeader,
newDecoder,
newExec) = newLoadStoreBase(name, Name, imm,
eaCode, accCode,
memFlags, instFlags,
base, execTemplateBase = 'Store')
newExec) = loadStoreBase(name, Name, imm,
eaCode, accCode,
memFlags, instFlags,
base, execTemplateBase = 'Store')
header_output += newHeader
decoder_output += newDecoder
@@ -95,7 +95,7 @@ let {{
accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewImm", post, writeback)
base = buildMemBase("MemoryImm", post, writeback)
emitStore(name, Name, True, eaCode, accCode, [], [], base)
@@ -120,7 +120,7 @@ let {{
accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewReg", post, writeback)
base = buildMemBase("MemoryReg", post, writeback)
emitStore(name, Name, False, eaCode, accCode, [], [], base)
@@ -142,7 +142,7 @@ let {{
accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewImm", post, writeback)
base = buildMemBase("MemoryImm", post, writeback)
emitStore(name, Name, True, eaCode, accCode, [], [], base)
@@ -165,7 +165,7 @@ let {{
accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewReg", post, writeback)
base = buildMemBase("MemoryReg", post, writeback)
emitStore(name, Name, False, eaCode, accCode, [], [], base)