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ARM: Rename the RevOp base class to something more generic.

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This commit is contained in:
Gabe Black
2010-06-02 12:58:08 -05:00
parent f9d1bba22a
commit 6c1b10043f
4 changed files with 21 additions and 21 deletions
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2
src/arch/arm/insts/misc.cc
View File

@@ -144,7 +144,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

6
src/arch/arm/insts/misc.hh
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@@ -94,14 +94,14 @@ class MsrRegOp : public MsrBase
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RevOp : public PredOp
class RegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1) :
RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1) :
PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
{}

30
src/arch/arm/isa/insts/misc.isa
View File

@@ -122,11 +122,11 @@ let {{
uint32_t val = Op1;
Dest = swap_byte(val);
'''
revIop = InstObjParams("rev", "Rev", "RevOp",
revIop = InstObjParams("rev", "Rev", "RegRegOp",
{ "code": revCode,
"predicate_test": predicateTest }, [])
header_output += RevOpDeclare.subst(revIop)
decoder_output += RevOpConstructor.subst(revIop)
header_output += RegRegOpDeclare.subst(revIop)
decoder_output += RegRegOpConstructor.subst(revIop)
exec_output += PredOpExecute.subst(revIop)
rev16Code = '''
@@ -136,22 +136,22 @@ let {{
(bits(val, 31, 24) << 16) |
(bits(val, 23, 16) << 24);
'''
rev16Iop = InstObjParams("rev16", "Rev16", "RevOp",
rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
{ "code": rev16Code,
"predicate_test": predicateTest }, [])
header_output += RevOpDeclare.subst(rev16Iop)
decoder_output += RevOpConstructor.subst(rev16Iop)
header_output += RegRegOpDeclare.subst(rev16Iop)
decoder_output += RegRegOpConstructor.subst(rev16Iop)
exec_output += PredOpExecute.subst(rev16Iop)
revshCode = '''
uint16_t val = Op1;
Dest = sext<16>(swap_byte(val));
'''
revshIop = InstObjParams("revsh", "Revsh", "RevOp",
revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
{ "code": revshCode,
"predicate_test": predicateTest }, [])
header_output += RevOpDeclare.subst(revshIop)
decoder_output += RevOpConstructor.subst(revshIop)
header_output += RegRegOpDeclare.subst(revshIop)
decoder_output += RegRegOpConstructor.subst(revshIop)
exec_output += PredOpExecute.subst(revshIop)
rbitCode = '''
@@ -167,21 +167,21 @@ let {{
}
Dest = resTemp;
'''
rbitIop = InstObjParams("rbit", "Rbit", "RevOp",
rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
{ "code": rbitCode,
"predicate_test": predicateTest }, [])
header_output += RevOpDeclare.subst(rbitIop)
decoder_output += RevOpConstructor.subst(rbitIop)
header_output += RegRegOpDeclare.subst(rbitIop)
decoder_output += RegRegOpConstructor.subst(rbitIop)
exec_output += PredOpExecute.subst(rbitIop)
clzCode = '''
Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
'''
clzIop = InstObjParams("clz", "Clz", "RevOp",
clzIop = InstObjParams("clz", "Clz", "RegRegOp",
{ "code": clzCode,
"predicate_test": predicateTest }, [])
header_output += RevOpDeclare.subst(clzIop)
decoder_output += RevOpConstructor.subst(clzIop)
header_output += RegRegOpDeclare.subst(clzIop)
decoder_output += RegRegOpConstructor.subst(clzIop)
exec_output += PredOpExecute.subst(clzIop)
ssatCode = '''

4
src/arch/arm/isa/templates/misc.isa
View File

@@ -99,7 +99,7 @@ def template MsrImmConstructor {{
}
}};
def template RevOpDeclare {{
def template RegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
protected:
@@ -111,7 +111,7 @@ class %(class_name)s : public %(base_class)s
};
}};
def template RevOpConstructor {{
def template RegRegOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)