Commit Graph

11662 Commits

Author SHA1 Message Date
Gabe Black
e0039d1eab arch: Eliminate the GuestByteOrder constant.
Most ISAs used that constant exactly once, when setting up a Process.
This change just propogates the constant to the one place it's used. In
MIPS, the endianness is hard coded as little. There were some checks
which would change the behavior if the endianness was big. This change
removes that dead code. If someone wants to add support for big endian
MIPS, they can go back and add in the small bits of code that would be
required. It's likely the existing big endian support was incomplete and
not tested, so it's probably best for someone interested in it to start
fresh anyway.

Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40178
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-24 23:18:47 +00:00
Gabe Black
773368d68d arch-arm: Consolidate register related files into a directory.
Create a directory called "regs" which holds files, primarily headers,
related to registers, with the exception of registers.hh. Hopefully
registers.hh will go away in the not too distant future, removing this
exception.

Change-Id: I631423c2b09bbcd14b20001380270718aeca619e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41737
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-24 23:10:38 +00:00
Daecheol You
b42482a3d7 mem-garnet: Added packet distribution stats
Trace data and control traffic between all source-destination pairs.
This is for identifying packet distribution and bottleneck of the
interconnect network.

Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
JIRA: https://gem5.atlassian.net/browse/GEM5-861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40275
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-24 04:39:40 +00:00
Daniel R. Carvalho
219003c575 base-stats: Make Rate's compilation smarter
A Rate should be supplied units of different types.
Rates between units of the same type are Ratios,
and should be declared as such.

An exception is applied to Count and Unspecified,
since those units represent unknown underlying units.

Change-Id: I36ab7c73b239ccc86d866c5b38e14fd765bbbd0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43008
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-03-23 18:17:27 +00:00
Daniel R. Carvalho
aa07dbfba9 base-stats: Add unit test for Stats::Units
Add a unit test for base/stats/unit.hh.

Change-Id: I87f729928bb99c7f4d657bca0307955be933d3ed
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-03-23 17:09:13 +00:00
Daniel R. Carvalho
b2c0b191e1 misc: Fix coding style for union's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-03-23 16:26:04 +00:00
Daniel R. Carvalho
7f1de4e686 misc: Fix coding style for enum's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 16:26:04 +00:00
Gabe Black
08913caec2 arch,cpu,kern,sim: Eliminate the utility.hh switching header.
This header is no longer used. Remove the places where it's included,
and stop generating it. Also eliminate the now empty SPARC and Power
versions of the header.

Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:58 +00:00
Gabe Black
5ffd619d38 arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:33 +00:00
Gabe Black
2cb09e4042 arch,cpu: Collapse away TheISA::advancePC.
In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
2021-03-22 21:01:07 +00:00
Gabe Black
7ac67eaf1b mem: Fix style in addr_mapper.hh.
Change-Id: I3fd0bee6ac79e34034fbcc25e5da505cc3fc7181
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43345
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-21 02:49:45 +00:00
Bobby R. Bruce
af81ec9041 Merge "misc: Merge branch 'release-staging-v21-0' into develop" into develop 2021-03-19 21:13:58 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Giacomo Travaglini
588df4be85 configs, mem: MemInterface generating its own controller
We are adding a controller method to MemInterface objects making
them able to generate the appropriate memory controller.

This will bring the following benefits

a) Semplification: It will simplify MemConfig.config_mem
b) Reusability: Scripts not using config_mem
won't have to duplicate the if...else checks
c) Modularity: Users will be able to define their own
dram interfaces without needing to handle the mem_ctrl
mapping in the shared MemConfig.py module

Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42074
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 13:34:37 +00:00
Gabe Black
1c35c00c4f arch,cpu: Get rid of the RenameMode template class.
There is no way to make this sort of template work with more than one
ISA at a time, and it's also more complex than it needs to be,
particularly since the methods within it are never used in performance
critical code. Using virtual functions is also simpler and uses less
code.

Change-Id: I0baa1a651fa656420f6f90776572f8700a6d7cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40106
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 00:56:21 +00:00
Daniel R. Carvalho
54f5270949 base: Add unit test for base/logging
Add unit test for base/logging. logging.cc had to be split
in a file containing the mock functionality, and the gtest
logging functionality.

Change-Id: Ia890c06b44134b70eada7a9deadef882f00a5c27
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41398
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 22:25:17 +00:00
Daniel R. Carvalho
8deb205ea1 base: Add LOC to Loggers
Printing the line and the file that triggered a log
is useful for debugging.

Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 22:24:51 +00:00
Bobby R. Bruce
68064d8043 misc: Merge branch 'release-staging-v21-0' into develop
Change-Id: I0ad043ded56fb848e045057a1e7a56ea39797906
2021-03-18 11:13:14 -07:00
Daniel R. Carvalho
6a7403f1a2 sim: Move SimObjectResolver dependency to SimObject
Move SimObjectResolver dependency from CheckpointIn to
SimObject to reduce serialization tangling.

Change-Id: I9973bea0e3c6cabb0051a55dbf9aebef8a50fba8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38739
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 17:34:30 +00:00
Daniel R. Carvalho
6bbee0fbce base: Add default log functionality to Logger
The only difference between the NormalLogger and Logger is
a simple implementation for log(), which is then called by
the other loggers. Since this is common to everybody, move
this implementation to Logger and remove NormalLogger.

This makes it possible to test the NormalLoggers using the
current gtest logging framework.

Change-Id: I6805fa14f58ddc7d37b00fcd7fcacb32e0b5d456
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41395
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-03-18 17:32:22 +00:00
Daniel R. Carvalho
763239ac32 base: Fix incorrect use of Logger::print
Previously when a formatted message was printed in a
Logger it would use the wrong function, and thus skip
the warning triggered by ccprintf. Fix this by merging
two prints to avoid ambiguity.

Change-Id: Idc51d2ef28ab4721d2be16f3e5fce19c494a0d47
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 17:32:22 +00:00
Yu-hsin Wang
a70dc125d1 sim: Add a copied symbol table for the kernel on physical address
In fs simulation, the kernel is loaded to physical address first and
then it would relocate itself to virtual address. The address which
using by kernel symbol table is virtual address. To debug the process
before kernel relocated to virutal memory, we need another copy of
symbol table for physical address.

Change-Id: I38107ff94b301df1a5170dd98774df88cfb02298
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43104
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 13:44:18 +00:00
Yu-hsin Wang
397b10957c base: Add a rename helper to SymbolTable
In some cases, we want to move and copy the symbol table to another
address. However, the name of symbol table should be unique. This rename
helper provides a way to modify the name of symbol. Developers can use
it to solve the conflict with this helper.

Change-Id: I4627e06da3a03da57009d613188be117c75750a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43105
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 08:05:24 +00:00
Daniel R. Carvalho
68d612c330 base-stats: Fix Watt Unit
Watt had two implementations. Since having the unit
printed as Watt is more relevant than as Joule/Second,
keep the class.

Change-Id: Ic9ae755115e2eca94492f3d5b11245db9fe42bb6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43006
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 13:53:15 +00:00
Tiago Mück
b13b485095 configs,mem-ruby: CHI-based Ruby protocol
This patch add a new Ruby cache coherence protocol based on Arm' AMBA5
CHI specification. The CHI protocol defines and implements two state
machine types:

- Cache_Controller: generic cache controller that can be configured as:
    - Top-level L1 I/D cache
    - A intermediate level (L2, L3, ...) private or shared cache
    - A CHI home node (i.e. the point of coherence of the system and
        has the global directory)
    - A DMA requester

- Memory_Controller: implements a CHI slave node and interfaces with
    gem5 memory controller. This controller has the functionality of a
    Directory_Controller on the other Ruby protocols, except it doesn't
    have a directory.

The Cache_Controller has multiple cache allocation/deallocation
parameters to control the clusivity with respect to upstream caches.
Allocation can be completely disabled to use Cache_Controller as a
DMA requester or as a home node without a shared LLC.

The standard configuration file configs/ruby/CHI.py provides a
'create_system' compatible with configs/example/fs.py and
configs/example/se.py and creates a system with private L1/L2 caches
per core and a shared LLC at the home nodes. Different cache topologies
can be defined by modifying 'create_system' or by creating custom
scripts using the structures defined in configs/ruby/CHI.py.

This patch also includes the 'CustomMesh' topology script to be used
with CHI. CustomMesh generates a 2D mesh topology with the placement
of components manually defined in a separate configuration file using
the --noc-config parameter.
The example in configs/example/noc_config/2x4.yaml creates a simple 2x4
mesh. For example, to run a SE mode simulation, with 4 cores,
4 mem ctnrls, and 4 home nodes (L3 caches):

build/ARM/gem5.opt configs/example/se.py \
--cmd 'tests/test-progs/hello/bin/arm/linux/hello' \
--ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \
--topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml

If one doesn't care about the component placement on the interconnect,
the 'Crossbar' and 'Pt2Pt' may be used and they do not require the
--noc-config option.

Additional authors:
    Joshua Randall <joshua.randall@arm.com>
    Pedro Benedicte <pedro.benedicteillescas@arm.com>
    Tuan Ta <tuan.ta2@arm.com>

JIRA: https://gem5.atlassian.net/browse/GEM5-908

Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42563
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 15:28:44 +00:00
Tiago Mück
dcc2f4caaf scons,mem-ruby: export need_partial_func_reads in SConstruct
need_partial_func_reads should now be modified from protocol specific
files (e.g. src/learning_gem5/part3/SConsopts)

Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 15:28:44 +00:00
Gabe Black
d79d8498a4 cpu: Use a unique_ptr to manage cached disassembly.
This is a fairly minor improvement, but avoids having to manually keep
track of that string pointer.

Change-Id: Ic3d4ddd9445920a110b36ab0cd64ff2289cf0139
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 11:04:39 +00:00
Gabe Black
c0317722ec dev: Clean up the VirtIO9PDiod::startDiod method.
Rather than print the errno, print the result of strerror so the user
doesn't have to look up what each error code does. Don't duplicate
descriptors needlessly which have been returned by pipe(). Use panic_if
instead of if () panic. Check each call to a standard library function
instead of calling multiple and then only knowing that one of them
failed (but not which one). Close the far side of our pipes for both
the gem5 process, and the process that will become diod. Remove some
stray #undef-s which undefine macros that were never defined. Don't
try to force the descriptors going to diod to be particular numbers.
Slightly reduce nesting in the if which checks the results of fork.
Drop unnecessary \n-s in calls to panic, inform, etc. Minor spacing
related style fixes. Use nullptr instead of NULL.

Change-Id: I48d93778a1e139ef624876a0b316486aac774d7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43083
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:46:53 +00:00
Giacomo Travaglini
9ffcf15471 dev-arm: Remove unused SMMUv3 WalkCache variables
Those were grouped within the stats data structures but were
not actually stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I01bbbada423825ded04a033c0709108e2980ec70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42985
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Giacomo Travaglini
d8b172917a dev-arm: Fix WalkCache stats
The WalkCache stats are wrongly using the legacy framework.
With this patch we are registering those to the hierarchical structure.

As we need to pass the Stats::Group parent at construction time,
we are replacing 2d arrays with Vector2d for count stats and using a flat
vector of pointers for the Formula stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8992bc262a376e4e81a4d608c11dff6902e0a01d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42984
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Giacomo Travaglini
1806525833 dev-arm: Fix SMMUv3BaseCache Stats
After [1] the SMMUv3BaseCache stats are undistinguible within each
other.

With this patch we are adding a string to their constructor so
that we can distinguish between an IPA, Config etc cache stat

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/36415

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iaa84ed948cf2a4c36ea4fcda589676b9bbeed6fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Gabe Black
10b0aceeff cpu: Narrow the dependencies of the StaticInst class.
Include only the minimal number of headers to make StaticInst subclasses
easier to test with unit tests.

Change-Id: Ie2e1c01b77d1776b366d29982e481d62b6a2b8cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42965
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 03:51:15 +00:00
Gabe Black
e1f2608141 cpu: Fix transitive includes in the O3 rename map and debug faults.
Change-Id: I22f80c24c3128e91fd039b8e3b689d7065440ad0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42964
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 03:51:07 +00:00
Gabe Black
122ff006c3 cpu: Fix some minor style issues in cpu/static_inst.hh.
Also use default values for some members rather than setting them in the
constructor explicitly.

Change-Id: I0f75cca54f952542d1f37576bd752a8d6acb5561
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42963
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 03:50:34 +00:00
Daniel R. Carvalho
eb9e11ad96 base: Move Named class to its own file
Named can be useful in instances where trace is not required.
Because of that it has been moved to its own file.

Named is intended for public inheritance; thus it should have
a virtual destructor.

Added a unit test for the Named class.

Change-Id: I314e850b4fafd7804d919fd3fe6dec44822e1f48
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38743
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 03:28:52 +00:00
Daniel R. Carvalho
be37868ca6 base: Add fatal tests to sat_counter
Add tests to make sure that the fatal conditions are
triggered when met.

This commit also moves shift-related death tests to
their own DeathTests.

Change-Id: Ia610636fe8cf636401e2b2ed623bf20b41147ea4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42763
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 03:01:36 +00:00
Adrian Herrera
89958f7f30 python: debug, fix Mapping import
Change "collections.Mapping" to "collections.abc.Mapping".
"collections.Mapping" was an alias, it is deprecated starting from Python 3.3, and it will be removed in Python 3.10.

Change-Id: Ic257e3c5206eb3d48d4eed85a93fac48bd3b8dc4
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43023
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-15 20:35:42 +00:00
Gabe Black
0a9dfbb8da arch: Remove copyMiscRegs from utility.hh.
This function is occasionally used internally in copyRegs, but is not
used by anything else and doesn't need to be publically exposed in the
header file.

Change-Id: Id02a77e7dd19c6c089a408bfe0099466822c523d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39325
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-13 22:27:00 +00:00
Kyle Roarty
352ce704f1 arch-x86: Add insts used in newer libstdc++ rehashing
For newer versions of libstdc++ (Like the one in the
ubuntu-20.04_all-dependencies docker image), the variables used when
rehashing, e.g., std::unordered_maps have been extended. This resulted
in the rehashing function using different, unimplemented, instructions.

Because these instructions are unimplemented, it resulted in a
std::bad_alloc exception when inserting into an unordered_map

This patchset implements the following instructions:
FCOMI, a floating point comparison instruction, using the compfp
microop. The implementation mirrors that of the FUCOMI instruction
(another floating point comparison instruction)

FSUBRP, a reverse subtraction instruction, is implemented using the
subfp microop like the FSUBP does, but with the operands flipped
accordingly.

FISTP, an instruction to convert a float to int and then store, is
implemented by using a conversion microop (cvtf_d2i) and then a store.
The cvtf_d2i microop is re-written to handle multple data sizes, as is
required by the FISTP instruction.

Change-Id: I85c57acace1f7a547b0a97ec3a0f0500909c5d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42443
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-13 18:18:27 +00:00
Maximilian Stein
e24d4b8659 arch-x86: Add allocator for ACPI tables
This adds an allocator class to allocate memory linearly. It is intended
to be used by ACPI tables to dynamically request memory to write the
ACPI tables to.

Change-Id: I43c71d2b8e676f8ac0fd08b9468b00b6212d85b6
Signed-off-by: Maximilian Stein <m@steiny.biz>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42823
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-13 13:30:15 +00:00
Peter Yuen
975fcf1355 arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Added takeover methods for PMA Checker and RiscvTLB to ensure
that checkpoint restoration works. Also added logic in PLIC
to prevent posting interrupts to a CPU that has yet to complete
the current interrupt. PLIC's behaviour when a CPU claims another
interrupt before completion is also changed. Now PLIC will return
the uncompleted interrupt ID instead of return 0. This behaviour
is not documented in the specs but is designed this way to avoid
issues from CPU side (especially MinorCPU).

Change-Id: I68eaaf56d2c4d76cc1e0a1e2160f5abe184c2cd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41933
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
2021-03-13 08:06:29 +00:00
Gabe Black
b22b7f2d66 arch,cpu: Move buildRetPC into the StaticInst class.
This was an inline function defined for each ISA, but really it makes
more sense for it to be defined by the instruction classes. The actual
return address for any given instruction can best be calculated when you
know what that instruction actually does, and also the instructions will
know about ISA level PC management.

Change-Id: I2c5203aefa90f2f26ecd94e82b925c6b552e33d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39324
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-13 05:53:27 +00:00
Yu-hsin Wang
60481e5111 cpu-kvm,arch-arm: correct arm kvm virtual time
According to the kernel code*1, the virtual time is related to physical
timer and cntvoff. When the simulator goes from KVM to gem5, the
physical timer is still ticking. After gem5 simulating models and going
back to KVM, the virtual time also goes away. We should update cntvoff
by ourselve to get correct virtual time.

Moreover, according to update_vtimer_cntvoff*2, setting cntvoff affacts
all vcpus. Instead of puting individual vtime on BaseArmKvmCPU, we
maintain a global vtime, restore it before the first vcpu going into
KVM, and save it after the last vcpu back from KVM.

1. https://code.woboq.org/linux/linux/virt/kvm/arm/arch_timer.c.html#826
2. https://code.woboq.org/linux/linux/virt/kvm/arm/arch_timer.c.html#update_vtimer_cntvoff

Change-Id: Ie054104642f2a6d5a0740f39b947f5f2c29c36f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42161
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-12 02:46:11 +00:00
Yu-hsin Wang
bf91a33e2d cpu-kvm: refactor x86 fixup before kvm_run
Since kvmRun still does lots of thing before really going to KVM, to
make the fixup more precise, I change ioctlRun to a virtual function and
make the derived class overrides it if needed.

Change-Id: Ifd75decf0a5445a5266398caebd8aac1a5e80c50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42301
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-03-12 02:46:11 +00:00
Gabe Black
7bb690c1ee scons,python: Always generate default create() methods.
We were originally generating default create() methods along side the
pybind definitions, but unfortunately those are only included when
python support is included. Since the SimObject Param structs are
unconditionally provided even if the thing calling their create()
methods is not, we need to also unconditionally provide the default
create() definitions. We do that by putting them in their own new .cc
files.

Change-Id: I29d1573d578794b3fe7ec2bc16ef5c8c58e56d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42589
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-03-11 22:54:05 +00:00
Gabe Black
6572078a99 cpu: Delete unnecessary create() methods.
These were added in changes which were created before create() methods
were mostly automated, but were checked in after the then unnecessary
create() methods were purged.

Change-Id: I03da797ae8328fab6ef6b85dbc4ea86b34512fd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42743
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 22:53:53 +00:00
Giacomo Travaglini
640de810cb base: Disable Death test for fast builds
The test would otherwise fail as the expected assertion
is stripped out of the build.

Change-Id: I7c1238b43ee86ad82ad89251754e4c804d8bf16d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42623
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 22:02:14 +00:00
Kyle Roarty
90d2aac515 mem-ruby: Add missing transitions + wakes for Dma events
This also changes one of the wakeUpDependents calls to a
wakeUpAllDependentsAddr call to prevent a hang.

Change-Id: Ia076414e5c6d9c8c0b2576d1f442195d75d275fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42463
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 21:16:22 +00:00
Gabe Black
6b1f8de43a base: Stop using testing::internal:: in tests.
The name strongly suggests that this namespace isn't for our use.
Instead, use the new gtestLogOutput string stream, or in the debug test
add an optional parameter to debugDumpFlags which lets us direct the
output to a string stream we can inspect.

Change-Id: I51d3c0ec42981b70736e7b3bbedfb49f82dc7f95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42723
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 16:30:02 +00:00