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mem-ruby: Add missing transitions + wakes for Dma events

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This also changes one of the wakeUpDependents calls to a
wakeUpAllDependentsAddr call to prevent a hang.

Change-Id: Ia076414e5c6d9c8c0b2576d1f442195d75d275fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42463
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Kyle Roarty
2021-03-07 17:20:27 -06:00
committed by Matt Sinclair
parent 6b1f8de43a
commit 90d2aac515
1 changed files with 3 additions and 2 deletions
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5
src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
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@@ -1119,7 +1119,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
// The exit state is always going to be U, so wakeUpDependents logic should be covered in all the
// transitions which are flowing into U.
transition({BL, BS_M, BM_M, B_M, BP, BDW_P, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B}, {DmaRead,DmaWrite}){
transition({BL, BDR_M, BS_M, BM_M, B_M, BP, BDR_PM, BDW_P, BS_PM, BM_PM, B_PM, BDR_Pm, BS_Pm, BM_Pm, B_Pm, B}, {DmaRead,DmaWrite}){
sd_stallAndWaitRequest;
}
@@ -1280,6 +1280,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
transition(BDR_M, MemData, U) {
mt_writeMemDataToTBE;
dd_sendResponseDmaData;
wa_wakeUpAllDependentsAddr;
dt_deallocateTBE;
pm_popMemQueue;
}
@@ -1373,7 +1374,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
dd_sendResponseDmaData;
// Check for pending requests from the core we put to sleep while waiting
// for a response
wa_wakeUpDependents;
wa_wakeUpAllDependentsAddr;
dt_deallocateTBE;
pt_popTriggerQueue;
}