From 90d2aac5153d6b8f769c29ff9ffc77a3411d8247 Mon Sep 17 00:00:00 2001 From: Kyle Roarty Date: Sun, 7 Mar 2021 17:20:27 -0600 Subject: [PATCH] mem-ruby: Add missing transitions + wakes for Dma events This also changes one of the wakeUpDependents calls to a wakeUpAllDependentsAddr call to prevent a hang. Change-Id: Ia076414e5c6d9c8c0b2576d1f442195d75d275fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42463 Reviewed-by: Matt Sinclair Reviewed-by: Matthew Poremba Maintainer: Matt Sinclair Tested-by: kokoro --- src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm index 684d03e3ce..4d24891b51 100644 --- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm +++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm @@ -1119,7 +1119,7 @@ machine(MachineType:Directory, "AMD Baseline protocol") // The exit state is always going to be U, so wakeUpDependents logic should be covered in all the // transitions which are flowing into U. - transition({BL, BS_M, BM_M, B_M, BP, BDW_P, BS_PM, BM_PM, B_PM, BS_Pm, BM_Pm, B_Pm, B}, {DmaRead,DmaWrite}){ + transition({BL, BDR_M, BS_M, BM_M, B_M, BP, BDR_PM, BDW_P, BS_PM, BM_PM, B_PM, BDR_Pm, BS_Pm, BM_Pm, B_Pm, B}, {DmaRead,DmaWrite}){ sd_stallAndWaitRequest; } @@ -1280,6 +1280,7 @@ machine(MachineType:Directory, "AMD Baseline protocol") transition(BDR_M, MemData, U) { mt_writeMemDataToTBE; dd_sendResponseDmaData; + wa_wakeUpAllDependentsAddr; dt_deallocateTBE; pm_popMemQueue; } @@ -1373,7 +1374,7 @@ machine(MachineType:Directory, "AMD Baseline protocol") dd_sendResponseDmaData; // Check for pending requests from the core we put to sleep while waiting // for a response - wa_wakeUpDependents; + wa_wakeUpAllDependentsAddr; dt_deallocateTBE; pt_popTriggerQueue; }