misc: Fix coding style for enum's opening braces

The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/ccregs.hh

@@ -41,7 +41,8 @@
 namespace ArmISA
 {
 
-enum ccRegIndex {
+enum ccRegIndex
+{
     CCREG_NZ,
     CCREG_C,
     CCREG_V,
@@ -60,7 +61,8 @@ const char * const ccRegName[NUM_CCREGS] = {
     "zero"
 };
 
-enum ConditionCode {
+enum ConditionCode
+{
     COND_EQ  =   0,
     COND_NE, //  1
     COND_CS, //  2

src/arch/arm/freebsd/freebsd.hh

@@ -255,7 +255,8 @@ class ArmFreebsd64 : public ArmFreebsd
     //@}
 
     /// Resource enumeration for getrlimit().
-    enum rlimit_resources {
+    enum rlimit_resources
+    {
         TGT_RLIMIT_CPU = 0,
         TGT_RLIMIT_FSIZE = 1,
         TGT_RLIMIT_DATA = 2,

src/arch/arm/insts/fplib.hh

@@ -54,7 +54,8 @@
 namespace ArmISA
 {
 
-enum FPRounding {
+enum FPRounding
+{
     FPRounding_TIEEVEN = 0,
     FPRounding_POSINF = 1,
     FPRounding_NEGINF = 2,

src/arch/arm/insts/macromem.hh

@@ -438,7 +438,8 @@ class MacroMemOp : public PredMacroOp
 class PairMemOp : public PredMacroOp
 {
   public:
-    enum AddrMode {
+    enum AddrMode
+    {
         AddrMd_Offset,
         AddrMd_PreIndex,
         AddrMd_PostIndex

src/arch/arm/insts/mem.hh

@@ -70,7 +70,8 @@ class MightBeMicro : public PredOp
 class RfeOp : public MightBeMicro
 {
   public:
-    enum AddrMode {
+    enum AddrMode
+    {
         DecrementAfter,
         DecrementBefore,
         IncrementAfter,
@@ -115,7 +116,8 @@ class RfeOp : public MightBeMicro
 class SrsOp : public MightBeMicro
 {
   public:
-    enum AddrMode {
+    enum AddrMode
+    {
         DecrementAfter,
         DecrementBefore,
         IncrementAfter,
@@ -155,7 +157,8 @@ class SrsOp : public MightBeMicro
 class Memory : public MightBeMicro
 {
   public:
-    enum AddrMode {
+    enum AddrMode
+    {
         AddrMd_Offset,
         AddrMd_PreIndex,
         AddrMd_PostIndex

src/arch/arm/insts/mem64.hh

@@ -87,7 +87,8 @@ class MightBeMicro64 : public ArmStaticInst
 class Memory64 : public MightBeMicro64
 {
   public:
-    enum AddrMode {
+    enum AddrMode
+    {
         AddrMd_Offset,
         AddrMd_PreIndex,
         AddrMd_PostIndex

src/arch/arm/insts/sve.hh

@@ -42,7 +42,8 @@
 
 namespace ArmISA {
 
-enum class SvePredType {
+enum class SvePredType
+{
     NONE,
     MERGE,
     ZERO,
@@ -581,11 +582,12 @@ class SveIntCmpImmOp : public ArmStaticInst
 class SveAdrOp : public ArmStaticInst
 {
   public:
-   enum SveAdrOffsetFormat {
-       SveAdrOffsetPacked,
-       SveAdrOffsetUnpackedSigned,
-       SveAdrOffsetUnpackedUnsigned
-   };
+    enum SveAdrOffsetFormat
+    {
+        SveAdrOffsetPacked,
+        SveAdrOffsetUnpackedSigned,
+        SveAdrOffsetUnpackedUnsigned
+    };
 
   protected:
     IntRegIndex dest, op1, op2;

src/arch/arm/insts/vfp.hh

@@ -48,7 +48,8 @@
 namespace ArmISA
 {
 
-enum VfpMicroMode {
+enum VfpMicroMode
+{
     VfpNotAMicroop,
     VfpMicroop,
     VfpFirstMicroop,

src/arch/arm/interrupts.hh

@@ -119,7 +119,8 @@ class Interrupts : public BaseInterrupts
         memset(interrupts, 0, sizeof(interrupts));
     }
 
-    enum InterruptMask {
+    enum InterruptMask
+    {
         INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
         INT_MASK_T, // taken regardless of mask
         INT_MASK_P  // pending

src/arch/arm/linux/linux.hh

@@ -417,7 +417,8 @@ class ArmLinux64 : public ArmLinux
     static const int TBL_SYSINFO = 12;
 
     /// Resource enumeration for getrlimit().
-    enum rlimit_resources {
+    enum rlimit_resources
+    {
         TGT_RLIMIT_CPU = 0,
         TGT_RLIMIT_FSIZE = 1,
         TGT_RLIMIT_DATA = 2,

src/arch/arm/miscregs.hh

@@ -53,7 +53,8 @@ class ThreadContext;
 
 namespace ArmISA
 {
-    enum MiscRegIndex {
+    enum MiscRegIndex
+    {
         MISCREG_CPSR = 0,
         MISCREG_SPSR,
         MISCREG_SPSR_FIQ,
@@ -1092,7 +1093,8 @@ namespace ArmISA
         NUM_MISCREGS
     };
 
-    enum MiscRegInfo {
+    enum MiscRegInfo
+    {
         MISCREG_IMPLEMENTED,
         MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
                                 // arch generic counter)

src/arch/arm/nativetrace.hh

@@ -38,7 +38,8 @@ namespace Trace {
 class ArmNativeTrace : public NativeTrace
 {
   public:
-    enum StateID {
+    enum StateID
+    {
         STATE_R0,
         STATE_R1,
         STATE_R2,

src/arch/arm/pagetable.hh

@@ -69,7 +69,8 @@ struct PTE
 };
 
 // Lookup level
-enum LookupLevel {
+enum LookupLevel
+{
     L0 = 0,  // AArch64 only
     L1,
     L2,
@@ -81,13 +82,15 @@ enum LookupLevel {
 struct TlbEntry : public Serializable
 {
   public:
-    enum class MemoryType : std::uint8_t {
+    enum class MemoryType : std::uint8_t
+    {
         StronglyOrdered,
         Device,
         Normal
     };
 
-    enum class DomainType : std::uint8_t {
+    enum class DomainType : std::uint8_t
+    {
         NoAccess = 0,
         Client,
         Reserved,

src/arch/arm/process.cc

@@ -146,7 +146,8 @@ ArmProcess64::initState()
 uint32_t
 ArmProcess32::armHwcapImpl() const
 {
-    enum ArmCpuFeature {
+    enum ArmCpuFeature
+    {
         Arm_Swp = 1 << 0,
         Arm_Half = 1 << 1,
         Arm_Thumb = 1 << 2,
@@ -174,7 +175,8 @@ ArmProcess64::armHwcapImpl() const
 {
     // In order to know what these flags mean, please refer to Linux
     // /Documentation/arm64/elf_hwcaps.txt text file.
-    enum ArmCpuFeature {
+    enum ArmCpuFeature
+    {
         Arm_Fp = 1 << 0,
         Arm_Asimd = 1 << 1,
         Arm_Evtstrm = 1 << 2,

src/arch/arm/semihosting.hh

@@ -197,7 +197,8 @@ class ArmSemihosting : public SimObject
         }
     };
 
-    enum Operation {
+    enum Operation
+    {
         SYS_OPEN = 0x01,
         SYS_CLOSE = 0x02,
         SYS_WRITEC = 0x03,

src/arch/arm/table_walker.hh

@@ -94,7 +94,8 @@ class TableWalker : public ClockedObject
     {
       public:
         /** Type of page table entry ARM DDI 0406B: B3-8*/
-        enum EntryType {
+        enum EntryType
+        {
             Ignore,
             PageTable,
             Section,
@@ -367,7 +368,8 @@ class TableWalker : public ClockedObject
     };
 
     // Granule sizes for AArch64 long descriptors
-    enum GrainSize {
+    enum GrainSize
+    {
         Grain4KB  = 12,
         Grain16KB = 14,
         Grain64KB = 16,
@@ -379,7 +381,8 @@ class TableWalker : public ClockedObject
     {
       public:
         /** Descriptor type */
-        enum EntryType {
+        enum EntryType
+        {
             Invalid,
             Table,
             Block,

src/arch/arm/tlb.hh

@@ -109,7 +109,8 @@ class TlbTestInterface
 class TLB : public BaseTLB
 {
   public:
-    enum ArmFlags {
+    enum ArmFlags
+    {
         AlignmentMask = 0x7,
 
         AlignByte = 0x0,
@@ -124,7 +125,8 @@ class TLB : public BaseTLB
         UserMode = 0x10
     };
 
-    enum ArmTranslationType {
+    enum ArmTranslationType
+    {
         NormalTran = 0,
         S1CTran = 0x1,
         HypMode = 0x2,

src/arch/arm/tracers/tarmac_base.hh

@@ -63,7 +63,8 @@ class TarmacBaseRecord : public InstRecord
 {
   public:
     /** TARMAC trace record type. */
-    enum TarmacRecordType {
+    enum TarmacRecordType
+    {
         TARMAC_INST,
         TARMAC_REG,
         TARMAC_MEM,
@@ -97,7 +98,8 @@ class TarmacBaseRecord : public InstRecord
     /** TARMAC register trace record. */
     struct RegEntry
     {
-        enum RegElement {
+        enum RegElement
+        {
             Lo = 0,
             Hi = 1,
             // Max = (max SVE vector length) 2048b / 64 = 32

src/arch/arm/types.hh

@@ -217,7 +217,8 @@ namespace ArmISA
 
         typedef GenericISA::UPCState<MachInst> Base;
 
-        enum FlagBits {
+        enum FlagBits
+        {
             ThumbBit = (1 << 0),
             JazelleBit = (1 << 1),
             AArch64Bit = (1 << 2)
@@ -564,7 +565,8 @@ namespace ArmISA
     };
 
     // Shift types for ARM instructions
-    enum ArmShiftType {
+    enum ArmShiftType
+    {
         LSL = 0,
         LSR,
         ASR,
@@ -572,7 +574,8 @@ namespace ArmISA
     };
 
     // Extension types for ARM instructions
-    enum ArmExtendType {
+    enum ArmExtendType
+    {
         UXTB = 0,
         UXTH = 1,
         UXTW = 2,
@@ -618,14 +621,16 @@ namespace ArmISA
         RND_NEAREST
     };
 
-    enum ExceptionLevel {
+    enum ExceptionLevel
+    {
         EL0 = 0,
         EL1,
         EL2,
         EL3
     };
 
-    enum OperatingMode {
+    enum OperatingMode
+    {
         MODE_EL0T = 0x0,
         MODE_EL1T = 0x4,
         MODE_EL1H = 0x5,
@@ -645,7 +650,8 @@ namespace ArmISA
         MODE_MAXMODE = MODE_SYSTEM
     };
 
-    enum ExceptionClass {
+    enum ExceptionClass
+    {
         EC_INVALID                 = -1,
         EC_UNKNOWN                 = 0x0,
         EC_TRAPPED_WFI_WFE         = 0x1,
@@ -700,7 +706,8 @@ namespace ArmISA
     /**
      * Instruction decoder fault codes in ExtMachInst.
      */
-    enum DecoderFault : std::uint8_t {
+    enum DecoderFault : std::uint8_t
+    {
         OK = 0x0, ///< No fault
         UNALIGNED = 0x1, ///< Unaligned instruction fault
 

src/arch/mips/faults.hh

@@ -41,7 +41,8 @@ namespace MipsISA
 
 typedef Addr FaultVect;
 
-enum ExcCode {
+enum ExcCode
+{
     // A dummy value to use when the code isn't defined or doesn't matter.
     ExcCodeDummy = 0,
 

src/arch/mips/isa.hh

@@ -61,7 +61,8 @@ namespace MipsISA
         uint8_t numThreads;
         uint8_t numVpes;
 
-        enum BankType {
+        enum BankType
+        {
             perProcessor,
             perThreadContext,
             perVirtProcessor
@@ -111,7 +112,8 @@ namespace MipsISA
         bool cp0Updated;
 
         // Enumerated List of CP0 Event Types
-        enum CP0EventType {
+        enum CP0EventType
+        {
             UpdateCP0
         };
 

src/arch/mips/registers.hh

@@ -53,7 +53,8 @@ const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
 const uint32_t MIPS32_QNAN = 0x7fbfffff;
 const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
 
-enum FPControlRegNums {
+enum FPControlRegNums
+{
    FLOATREG_FIR = NumFloatArchRegs,
    FLOATREG_FCCR,
    FLOATREG_FEXR,
@@ -61,7 +62,8 @@ enum FPControlRegNums {
    FLOATREG_FCSR
 };
 
-enum FCSRBits {
+enum FCSRBits
+{
     Inexact = 1,
     Underflow,
     Overflow,
@@ -70,13 +72,15 @@ enum FCSRBits {
     Unimplemented
 };
 
-enum FCSRFields {
+enum FCSRFields
+{
     Flag_Field = 1,
     Enable_Field = 6,
     Cause_Field = 11
 };
 
-enum MiscIntRegNums {
+enum MiscIntRegNums
+{
    INTREG_LO = NumIntArchRegs,
    INTREG_DSP_LO0 = INTREG_LO,
    INTREG_HI,

src/arch/power/miscregs.hh

@@ -34,7 +34,8 @@
 namespace PowerISA
 {
 
-enum MiscRegIndex {
+enum MiscRegIndex
+{
     NUM_MISCREGS = 0
 };
 

src/arch/power/registers.hh

@@ -70,7 +70,8 @@ const int StackPointerReg = 1;
 // There isn't one in Power, but we need to define one somewhere
 const int ZeroReg = NumIntRegs - 1;
 
-enum MiscIntRegNums {
+enum MiscIntRegNums
+{
     INTREG_CR = NumIntArchRegs,
     INTREG_XER,
     INTREG_LR,

src/arch/riscv/faults.hh

@@ -41,7 +41,8 @@
 namespace RiscvISA
 {
 
-enum FloatException : uint64_t {
+enum FloatException : uint64_t
+{
     FloatInexact = 0x1,
     FloatUnderflow = 0x2,
     FloatOverflow = 0x4,
@@ -58,7 +59,8 @@ enum FloatException : uint64_t {
  * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
  * privileged specification v 1.10. Codes are enumerated in Table 3.6.
  */
-enum ExceptionCode : uint64_t {
+enum ExceptionCode : uint64_t
+{
     INST_ADDR_MISALIGNED = 0,
     INST_ACCESS = 1,
     INST_ILLEGAL = 2,

src/arch/riscv/pagetable_walker.hh

@@ -81,7 +81,8 @@ namespace RiscvISA
         {
           friend class Walker;
           private:
-            enum State {
+            enum State
+            {
                 Ready,
                 Waiting,
                 Translate,

src/arch/riscv/registers.hh

@@ -143,7 +143,8 @@ const std::vector<std::string> FloatRegNames = {
     "ft8", "ft9", "ft10", "ft11"
 };
 
-enum MiscRegIndex {
+enum MiscRegIndex
+{
     MISCREG_PRV = 0,
     MISCREG_ISA,
     MISCREG_VENDORID,
@@ -272,7 +273,8 @@ enum MiscRegIndex {
     NUM_MISCREGS
 };
 
-enum CSRIndex {
+enum CSRIndex
+{
     CSR_USTATUS = 0x000,
     CSR_UIE = 0x004,
     CSR_UTVEC = 0x005,

src/arch/sparc/asi.hh

@@ -32,7 +32,8 @@
 namespace SparcISA
 {
 
-enum ASI {
+enum ASI
+{
     ASI_IMPLICIT = 0x00,
     /* Priveleged ASIs */
     // 0x00-0x03 implementation dependent

src/arch/sparc/isa.hh

@@ -143,7 +143,8 @@ class ISA : public BaseISA
     static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
     static const int TotalWindowed = NWindows * RegsPerWindow;
 
-    enum InstIntRegOffsets {
+    enum InstIntRegOffsets
+    {
         CurrentGlobalsOffset = 0,
         CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
         MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,

src/arch/sparc/pagetable.hh

@@ -65,7 +65,8 @@ class TteTag
 class PageTableEntry
 {
   public:
-    enum EntryType {
+    enum EntryType
+    {
       sun4v,
       sun4u,
       invalid

src/arch/sparc/tlb.hh

@@ -79,7 +79,8 @@ class TLB : public BaseTLB
 
     std::list<TlbEntry*> freeList;
 
-    enum FaultTypes {
+    enum FaultTypes
+    {
         OtherFault = 0,
         PrivViolation = 0x1,
         SideEffect = 0x2,
@@ -90,13 +91,15 @@ class TLB : public BaseTLB
         VaOutOfRangeJmp = 0x40
     };
 
-    enum ContextType {
+    enum ContextType
+    {
         Primary = 0,
         Secondary = 1,
         Nucleus = 2
     };
 
-    enum TsbPageSize {
+    enum TsbPageSize
+    {
         Ps0,
         Ps1
     };

src/arch/x86/cpuid.cc

@@ -33,7 +33,8 @@
 #include "cpu/thread_context.hh"
 
 namespace X86ISA {
-    enum StandardCpuidFunction {
+    enum StandardCpuidFunction
+    {
         VendorAndLargestStdFunc,
         FamilyModelStepping,
         CacheAndTLB,
@@ -45,7 +46,8 @@ namespace X86ISA {
         NumStandardCpuidFuncs
     };
 
-    enum ExtendedCpuidFunctions {
+    enum ExtendedCpuidFunctions
+    {
         VendorAndLargestExtFunc,
         FamilyModelSteppingBrandFeatures,
         NameString1,

src/arch/x86/decoder.hh

@@ -181,7 +181,8 @@ class Decoder : public InstDecoder
     // for both the actual immediate and the displacement.
     int immediateCollected;
 
-    enum State {
+    enum State
+    {
         ResetState,
         FromCacheState,
         PrefixState,

src/arch/x86/decoder_tables.cc

@@ -164,7 +164,8 @@ namespace X86ISA
 /*  F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
     };
 
-    enum SizeType {
+    enum SizeType
+    {
         NoImm,
         NI = NoImm,
         ByteImm,

src/arch/x86/intmessage.hh

@@ -50,7 +50,8 @@ namespace X86ISA
 
     namespace DeliveryMode
     {
-        enum IntDeliveryMode {
+        enum IntDeliveryMode
+        {
             Fixed = 0,
             LowestPriority = 1,
             SMI = 2,

src/arch/x86/ldstflags.hh

@@ -48,7 +48,8 @@ namespace X86ISA
 {
     M5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4);
     const int FlagShift = 4;
-    enum FlagBit {
+    enum FlagBit
+    {
         CPL0FlagBit = 1,
         AddrSizeFlagBit = 2,
         StoreCheck = 4

src/arch/x86/pagetable_walker.hh

@@ -79,7 +79,8 @@ namespace X86ISA
         {
           friend class Walker;
           private:
-            enum State {
+            enum State
+            {
                 Ready,
                 Waiting,
                 // Long mode

src/arch/x86/process.cc

@@ -723,7 +723,8 @@ X86Process::argsInit(int pageSize,
     // We want 16 byte alignment
     uint64_t align = 16;
 
-    enum X86CpuFeature {
+    enum X86CpuFeature
+    {
         X86_OnboardFPU = 1 << 0,
         X86_VirtualModeExtensions = 1 << 1,
         X86_DebuggingExtensions = 1 << 2,

src/arch/x86/process.hh

@@ -50,7 +50,8 @@ class SyscallDesc;
 
 namespace X86ISA
 {
-    enum X86AuxiliaryVectorTypes {
+    enum X86AuxiliaryVectorTypes
+    {
         M5_AT_SYSINFO = 32,
         M5_AT_SYSINFO_EHDR = 33
     };

src/arch/x86/registers.hh

@@ -59,7 +59,8 @@ const int NumFloatRegs =
     NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
 
 // These enumerate all the registers for dependence tracking.
-enum DependenceTags {
+enum DependenceTags
+{
     // FP_Reg_Base must be large enough to be bigger than any integer
     // register index which has the IntFoldBit (1 << 6) set.  To be safe
     // we just start at (1 << 7) == 128.

src/arch/x86/regs/misc.hh

@@ -51,7 +51,8 @@
 
 namespace X86ISA
 {
-    enum CondFlagBit {
+    enum CondFlagBit
+    {
         CFBit = 1 << 0,
         PFBit = 1 << 2,
         ECFBit = 1 << 3,
@@ -66,7 +67,8 @@ namespace X86ISA
     const uint32_t cfofMask = CFBit | OFBit;
     const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
 
-    enum RFLAGBit {
+    enum RFLAGBit
+    {
         TFBit = 1 << 8,
         IFBit = 1 << 9,
         NTBit = 1 << 14,
@@ -78,7 +80,8 @@ namespace X86ISA
         IDBit = 1 << 21
     };
 
-    enum X87StatusBit {
+    enum X87StatusBit
+    {
         // Exception Flags
         IEBit = 1 << 0,
         DEBit = 1 << 1,

src/arch/x86/types.hh

@@ -52,7 +52,8 @@ namespace X86ISA
 //This really determines how many bytes are passed to the decoder.
 typedef uint64_t MachInst;
 
-enum Prefixes {
+enum Prefixes
+{
     NoOverride,
     ESOverride,
     CSOverride,
@@ -145,7 +146,8 @@ BitUnion8(VexInfo)
     Bitfield<0> present;
 EndBitUnion(VexInfo)
 
-enum OpcodeType {
+enum OpcodeType
+{
     BadOpcode,
     OneByteOpcode,
     TwoByteOpcode,
@@ -182,12 +184,14 @@ BitUnion8(OperatingMode)
     Bitfield<2,0> submode;
 EndBitUnion(OperatingMode)
 
-enum X86Mode {
+enum X86Mode
+{
     LongMode,
     LegacyMode
 };
 
-enum X86SubMode {
+enum X86SubMode
+{
     SixtyFourBitMode,
     CompatabilityMode,
     ProtectedMode,

src/base/loader/object_file.hh

@@ -41,7 +41,8 @@
 namespace Loader
 {
 
-enum Arch {
+enum Arch
+{
     UnknownArch,
     SPARC64,
     SPARC32,
@@ -58,7 +59,8 @@ enum Arch {
 
 const char *archToString(Arch arch);
 
-enum OpSys {
+enum OpSys
+{
     UnknownOpSys,
     Tru64,
     Linux,

src/base/loader/symtab.hh

@@ -44,7 +44,8 @@ namespace Loader
 
 struct Symbol
 {
-    enum class Binding {
+    enum class Binding
+    {
         Global,
         Local,
         Weak

src/base/logging.hh

@@ -61,7 +61,8 @@ class Logger
     static Logger &getInfo();
     static Logger &getHack();
 
-    enum LogLevel {
+    enum LogLevel
+    {
         PANIC, FATAL, WARN, INFO, HACK,
         NUM_LOG_LEVELS,
     };

src/base/remote_gdb.cc

@@ -283,7 +283,8 @@ hex2i(const char **srcp)
     return r;
 }
 
-enum GdbBreakpointType {
+enum GdbBreakpointType
+{
     GdbSoftBp = '0',
     GdbHardBp = '1',
     GdbWriteWp = '2',

src/base/vnc/vncinput.hh

@@ -87,7 +87,8 @@ class VncInput : public SimObject
   public:
 
     /** Client -> Server message IDs */
-    enum ClientMessages {
+    enum ClientMessages
+    {
         ClientSetPixelFormat    = 0,
         ClientSetEncodings      = 2,
         ClientFrameBufferUpdate = 3,

src/base/vnc/vncserver.hh

@@ -71,7 +71,8 @@ class VncServer : public VncInput
     const static uint32_t VncOK   = 0;
 
     /** Server -> Client message IDs */
-    enum ServerMessages {
+    enum ServerMessages
+    {
         ServerFrameBufferUpdate     = 0,
         ServerSetColorMapEntries    = 1,
         ServerBell                  = 2,
@@ -79,7 +80,8 @@ class VncServer : public VncInput
     };
 
     /** Encoding types */
-    enum EncodingTypes {
+    enum EncodingTypes
+    {
         EncodingRaw         = 0,
         EncodingCopyRect    = 1,
         EncodingHextile     = 5,
@@ -87,7 +89,8 @@ class VncServer : public VncInput
     };
 
     /** keyboard/mouse support */
-    enum MouseEvents {
+    enum MouseEvents
+    {
         MouseLeftButton     = 0x1,
         MouseRightButton    = 0x2,
         MouseMiddleButton   = 0x4
@@ -98,7 +101,8 @@ class VncServer : public VncInput
         return "RFB 003.008\n";
     }
 
-    enum ConnectionState {
+    enum ConnectionState
+    {
         WaitForProtocolVersion,
         WaitForSecurityResponse,
         WaitForClientInit,

src/cpu/base.hh

@@ -520,7 +520,8 @@ class BaseCPU : public ClockedObject
     ProbePointArg<bool> *ppSleeping;
     /** @} */
 
-    enum CPUState {
+    enum CPUState
+    {
         CPU_STATE_ON,
         CPU_STATE_SLEEP,
         CPU_STATE_WAKEUP

src/cpu/base_dyn_inst.hh

@@ -92,7 +92,8 @@ class BaseDynInst : public ExecContext, public RefCounted
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
   protected:
-    enum Status {
+    enum Status
+    {
         IqEntry,                 /// Instruction is in the IQ
         RobEntry,                /// Instruction is in the ROB
         LsqEntry,                /// Instruction is in the LSQ
@@ -121,7 +122,8 @@ class BaseDynInst : public ExecContext, public RefCounted
         NumStatus
     };
 
-    enum Flags {
+    enum Flags
+    {
         NotAnInst,
         TranslationStarted,
         TranslationCompleted,

src/cpu/inst_res.hh

@@ -55,7 +55,8 @@ class InstResult
         MultiResult() {}
     };
 
-    enum class ResultType {
+    enum class ResultType
+    {
         Scalar,
         VecElem,
         VecReg,

src/cpu/kvm/base.hh

@@ -175,7 +175,8 @@ class BaseKvmCPU : public BaseCPU
      *   }
      * @enddot
      */
-    enum Status {
+    enum Status
+    {
         /** Context not scheduled in KVM.
          *
          * The CPU generally enters this state when the guest execute

src/cpu/o3/commit.hh

@@ -108,7 +108,8 @@ class DefaultCommit
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         ROBSquashing,

src/cpu/o3/cpu.hh

@@ -104,7 +104,8 @@ class FullO3CPU : public BaseO3CPU
     friend class O3ThreadContext<Impl>;
 
   public:
-    enum Status {
+    enum Status
+    {
         Running,
         Idle,
         Halted,
@@ -537,7 +538,8 @@ class FullO3CPU : public BaseO3CPU
      *  activateStage() or deactivateStage(), they can specify which stage
      *  is being activated/deactivated.
      */
-    enum StageIdx {
+    enum StageIdx
+    {
         FetchIdx,
         DecodeIdx,
         RenameIdx,

src/cpu/o3/decode.hh

@@ -73,13 +73,15 @@ class DefaultDecode
     /** Overall decode stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum DecodeStatus {
+    enum DecodeStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         StartSquash,

src/cpu/o3/fetch.hh

@@ -172,13 +172,15 @@ class DefaultFetch
     /** Overall fetch status. Used to determine if the CPU can
      * deschedule itsef due to a lack of activity.
      */
-    enum FetchStatus {
+    enum FetchStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         Squashing,

src/cpu/o3/iew.hh

@@ -96,13 +96,15 @@ class DefaultIEW
     /** Overall IEW stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum Status {
+    enum Status
+    {
         Active,
         Inactive
     };
 
     /** Status for Issue, Execute, and Writeback stages. */
-    enum StageStatus {
+    enum StageStatus
+    {
         Running,
         Blocked,
         Idle,

src/cpu/o3/rename.hh

@@ -93,13 +93,15 @@ class DefaultRename
     /** Overall rename status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum RenameStatus {
+    enum RenameStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         StartSquash,
@@ -468,7 +470,8 @@ class DefaultRename
     /** Enum to record the source of a structure full stall.  Can come from
      * either ROB, IQ, LSQ, and it is priortized in that order.
      */
-    enum FullSource {
+    enum FullSource
+    {
         ROB,
         IQ,
         LQ,

src/cpu/o3/rob.hh

@@ -67,7 +67,8 @@ class ROB
     typedef typename std::list<DynInstPtr>::iterator InstIt;
 
     /** Possible ROB statuses. */
-    enum Status {
+    enum Status
+    {
         Running,
         Idle,
         ROBSquashing

src/cpu/reg_class.hh

@@ -49,7 +49,8 @@
 #include "config/the_isa.hh"
 
 /** Enumerate the classes of registers. */
-enum RegClass {
+enum RegClass
+{
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
     /** Vector Register. */

src/cpu/simple/base.hh

@@ -104,7 +104,8 @@ class BaseSimpleCPU : public BaseCPU
     StaticInstPtr curMacroStaticInst;
 
   protected:
-    enum Status {
+    enum Status
+    {
         Idle,
         Running,
         Faulting,

src/cpu/testers/gpu_ruby_test/episode.hh

@@ -50,7 +50,8 @@ class Episode
     class Action
     {
       public:
-        enum class Type {
+        enum class Type
+        {
             ACQUIRE,
             RELEASE,
             ATOMIC,

src/dev/arm/energy_ctrl.hh

@@ -97,7 +97,8 @@ class EnergyCtrl : public BasicPioDevice
      *       while (!read(PERF_LEVEL_ACK));
      */
 
-    enum Registers {
+    enum Registers
+    {
         DVFS_HANDLER_STATUS = 0,
         DVFS_NUM_DOMAINS,
         DVFS_DOMAINID_AT_INDEX,

src/dev/arm/flash_device.hh

@@ -68,7 +68,8 @@ class FlashDevice : public AbstractNVM
 
   private:
     /** Defines the possible actions to the flash*/
-    enum Actions {
+    enum Actions
+    {
         ActionRead,
         ActionWrite,
         ActionErase,

src/dev/arm/fvp_base_pwr_ctrl.hh

@@ -106,7 +106,8 @@ class FVPBasePwrCtrl : public BasicPioDevice
         Bitfield<0> pwk;
     EndBitUnion(PwrStatus)
 
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         PPOFFR = 0x00,
         PPONR  = 0x04,
         PCOFFR = 0x08,

src/dev/arm/hdlcd.hh

@@ -115,7 +115,8 @@ class HDLcd: public AmbaDmaDevice
 
   protected: // Register handling
     /** ARM HDLcd register offsets */
-    enum RegisterOffset {
+    enum RegisterOffset
+    {
         Version          = 0x0000,
         Int_RawStat      = 0x0010,
         Int_Clear        = 0x0014,

src/dev/arm/pl111.hh

@@ -97,7 +97,8 @@ class Pl111: public AmbaDmaDevice
 
     static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
 
-    enum LcdMode {
+    enum LcdMode
+    {
         bpp1 = 0,
         bpp2,
         bpp4,

src/dev/arm/rv_ctrl.hh

@@ -51,7 +51,8 @@
 class RealViewCtrl : public BasicPioDevice
 {
   public:
-    enum DeviceFunc {
+    enum DeviceFunc
+    {
         FUNC_OSC      = 1,
         FUNC_VOLT     = 2,
         FUNC_AMP      = 3,

src/dev/arm/smmu_v3_caches.hh

@@ -94,7 +94,8 @@ class SMMUv3BaseCache
 class SMMUTLB : public SMMUv3BaseCache
 {
   public:
-    enum AllocPolicy {
+    enum AllocPolicy
+    {
         ALLOC_ANY_WAY,
         ALLOC_ANY_BUT_LAST_WAY,
         ALLOC_LAST_WAY,

src/dev/arm/smmu_v3_defs.hh

@@ -318,7 +318,8 @@ enum {
     CR0_VMW_MASK = 0x1C0,
 };
 
-enum SMMUCommandType {
+enum SMMUCommandType
+{
     CMD_PRF_CONFIG     = 0x01,
     CMD_PRF_ADDR       = 0x02,
     CMD_CFGI_STE       = 0x03,
@@ -373,11 +374,13 @@ struct SMMUCommand
     }
 };
 
-enum SMMUEventTypes {
+enum SMMUEventTypes
+{
     EVT_FAULT = 0x0001,
 };
 
-enum SMMUEventFlags {
+enum SMMUEventFlags
+{
     EVF_WRITE = 0x0001,
 };
 

src/dev/arm/smmu_v3_proc.hh

@@ -52,7 +52,8 @@ class SMMUv3DeviceInterface;
  * The meaning of these becomes apparent when you
  * look at runProcessAtomic()/runProcessTiming().
  */
-enum SMMUActionType {
+enum SMMUActionType
+{
     ACTION_INITIAL_NOP,
     ACTION_SEND_REQ,
     ACTION_SEND_REQ_FINAL,

src/dev/arm/ufs_device.hh

@@ -776,7 +776,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI command set; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSICommandSet {
+        enum SCSICommandSet
+        {
             SCSIInquiry = 0x12,
             SCSIRead6 = 0x08,
             SCSIRead10 = 0x28,
@@ -809,7 +810,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI status codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSIStatusCodes {
+        enum SCSIStatusCodes
+        {
             SCSIGood = 0x00,
             SCSICheckCondition = 0x02,
             SCSIConditionGood = 0x04,
@@ -827,7 +829,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI sense codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSISenseCodes {
+        enum SCSISenseCodes
+        {
             SCSINoSense = 0x00,
             SCSIRecoverdError = 0x01,
             SCSINotReady = 0x02,
@@ -1197,7 +1200,8 @@ class UFSHostDevice : public DmaDevice
      * http://www.jedec.org/standards-documents/results/jesd223
      * for their definition.
      */
-    enum UFSHCIRegisters {
+    enum UFSHCIRegisters
+    {
         regControllerCapabilities = 0x00,
         regUFSVersion = 0x08,
         regControllerDEVID = 0x10,

src/dev/arm/watchdog_sp805.hh

@@ -62,7 +62,8 @@ class Sp805 : public AmbaIntDevice
     Tick write(PacketPtr pkt) override;
 
   private:
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         WDOGLOAD      = 0x000,
         WDOGVALUE     = 0x004,
         WDOGCONTROL   = 0x008,

src/dev/hsa/hsa_signal.hh

@@ -35,7 +35,8 @@
 
 // AMD Signal Kind Enumeration Values.
 typedef int64_t amd_signal_kind64_t;
-enum amd_signal_kind_t {
+enum amd_signal_kind_t
+{
   AMD_SIGNAL_KIND_INVALID = 0,
   AMD_SIGNAL_KIND_USER = 1,
   AMD_SIGNAL_KIND_DOORBELL = -1,

src/dev/i2c/bus.hh

@@ -54,7 +54,8 @@ class I2CBus : public BasicPioDevice
 {
   protected:
 
-    enum I2CState {
+    enum I2CState
+    {
         IDLE,
         RECEIVING_ADDR,
         RECEIVING_DATA,

src/dev/intel_8254_timer.hh

@@ -50,21 +50,24 @@ class Intel8254Timer : public EventManager
         Bitfield<0> bcd;
     EndBitUnion(CtrlReg)
 
-    enum SelectVal {
+    enum SelectVal
+    {
         SelectCounter0,
         SelectCounter1,
         SelectCounter2,
         ReadBackCommand
     };
 
-    enum ReadWriteVal {
+    enum ReadWriteVal
+    {
         LatchCommand,
         LsbOnly,
         MsbOnly,
         TwoPhase
     };
 
-    enum ModeVal {
+    enum ModeVal
+    {
         InitTc,
         OneShot,
         RateGen,

src/dev/net/ns_gige_reg.h

@@ -35,7 +35,8 @@
 #define __DEV_NS_GIGE_REG_H__
 
 /* Device Register Address Map */
-enum DeviceRegisterAddress {
+enum DeviceRegisterAddress
+{
     CR =                0x00,
     CFGR =              0x04,
     MEAR =              0x08,
@@ -78,7 +79,8 @@ enum DeviceRegisterAddress {
 };
 
 /* Chip Command Register */
-enum ChipCommandRegister {
+enum ChipCommandRegister
+{
      CR_TXE =           0x00000001,
      CR_TXD =           0x00000002,
      CR_RXE =           0x00000004,
@@ -90,7 +92,8 @@ enum ChipCommandRegister {
 };
 
 /* configuration register */
-enum ConfigurationRegisters {
+enum ConfigurationRegisters
+{
      CFGR_ZERO =        0x00000000,
      CFGR_LNKSTS =      0x80000000,
      CFGR_SPDSTS =      0x60000000,
@@ -126,7 +129,8 @@ enum ConfigurationRegisters {
 };
 
 /* EEPROM access register */
-enum EEPROMAccessRegister {
+enum EEPROMAccessRegister
+{
      MEAR_EEDI =        0x00000001,
      MEAR_EEDO =        0x00000002,
      MEAR_EECLK =       0x00000004,
@@ -137,7 +141,8 @@ enum EEPROMAccessRegister {
 };
 
 /* PCI test control register */
-enum PCITestControlRegister {
+enum PCITestControlRegister
+{
      PTSCR_EEBIST_FAIL =        0x00000001,
      PTSCR_EEBIST_EN =          0x00000002,
      PTSCR_EELOAD_EN =          0x00000004,
@@ -149,7 +154,8 @@ enum PCITestControlRegister {
 };
 
 /* interrupt status register */
-enum InterruptStatusRegister {
+enum InterruptStatusRegister
+{
      ISR_RESERVE =      0x80000000,
      ISR_TXDESC3 =      0x40000000,
      ISR_TXDESC2 =      0x20000000,
@@ -192,7 +198,8 @@ enum InterruptStatusRegister {
 };
 
 /* transmit configuration register */
-enum TransmitConfigurationRegister {
+enum TransmitConfigurationRegister
+{
      TX_CFG_CSI =       0x80000000,
      TX_CFG_HBI =       0x40000000,
      TX_CFG_MLB =       0x20000000,
@@ -214,7 +221,8 @@ enum TransmitConfigurationRegister {
 };
 
 /*general purpose I/O control register */
-enum GeneralPurposeIOControlRegister {
+enum GeneralPurposeIOControlRegister
+{
      GPIOR_UNUSED =     0xffff8000,
      GPIOR_GP5_IN =     0x00004000,
      GPIOR_GP4_IN =     0x00002000,
@@ -234,7 +242,8 @@ enum GeneralPurposeIOControlRegister {
 };
 
 /* receive configuration register */
-enum ReceiveConfigurationRegister {
+enum ReceiveConfigurationRegister
+{
      RX_CFG_AEP =       0x80000000,
      RX_CFG_ARP =       0x40000000,
      RX_CFG_STRIPCRC =  0x20000000,
@@ -248,7 +257,8 @@ enum ReceiveConfigurationRegister {
 };
 
 /* pause control status register */
-enum PauseControlStatusRegister {
+enum PauseControlStatusRegister
+{
      PCR_PSEN =         (1 << 31),
      PCR_PS_MCAST =     (1 << 30),
      PCR_PS_DA =        (1 << 29),
@@ -260,7 +270,8 @@ enum PauseControlStatusRegister {
 };
 
 /*receive filter/match control register */
-enum ReceiveFilterMatchControlRegister {
+enum ReceiveFilterMatchControlRegister
+{
      RFCR_RFEN =        0x80000000,
      RFCR_AAB =         0x40000000,
      RFCR_AAM =         0x20000000,
@@ -279,14 +290,16 @@ enum ReceiveFilterMatchControlRegister {
 };
 
 /* receive filter/match data register */
-enum ReceiveFilterMatchDataRegister {
+enum ReceiveFilterMatchDataRegister
+{
      RFDR_BMASK =       0x00030000,
      RFDR_RFDATA0 =     0x000000ff,
      RFDR_RFDATA1 =     0x0000ff00
 };
 
 /* management information base control register */
-enum ManagementInformationBaseControlRegister {
+enum ManagementInformationBaseControlRegister
+{
      MIBC_MIBS =        0x00000008,
      MIBC_ACLR =        0x00000004,
      MIBC_FRZ =         0x00000002,
@@ -294,7 +307,8 @@ enum ManagementInformationBaseControlRegister {
 };
 
 /* VLAN/IP receive control register */
-enum VLANIPReceiveControlRegister {
+enum VLANIPReceiveControlRegister
+{
      VRCR_RUDPE =       0x00000080,
      VRCR_RTCPE =       0x00000040,
      VRCR_RIPE =        0x00000020,
@@ -306,7 +320,8 @@ enum VLANIPReceiveControlRegister {
 };
 
 /* VLAN/IP transmit control register */
-enum VLANIPTransmitControlRegister {
+enum VLANIPTransmitControlRegister
+{
      VTCR_PPCHK =       0x00000008,
      VTCR_GCHK =        0x00000004,
      VTCR_VPPTI =       0x00000002,
@@ -314,25 +329,29 @@ enum VLANIPTransmitControlRegister {
 };
 
 /* Clockrun Control/Status Register */
-enum ClockrunControlStatusRegister {
+enum ClockrunControlStatusRegister
+{
      CCSR_CLKRUN_EN =   0x00000001
 };
 
 /* TBI control register */
-enum TBIControlRegister {
+enum TBIControlRegister
+{
      TBICR_MR_LOOPBACK =        0x00004000,
      TBICR_MR_AN_ENABLE =       0x00001000,
      TBICR_MR_RESTART_AN =      0x00000200
 };
 
 /* TBI status register */
-enum TBIStatusRegister {
+enum TBIStatusRegister
+{
      TBISR_MR_LINK_STATUS =     0x00000020,
      TBISR_MR_AN_COMPLETE =     0x00000004
 };
 
 /* TBI auto-negotiation advertisement register */
-enum TBIAutoNegotiationAdvertisementRegister {
+enum TBIAutoNegotiationAdvertisementRegister
+{
      TANAR_NP =         0x00008000,
      TANAR_RF2 =        0x00002000,
      TANAR_RF1 =        0x00001000,
@@ -344,7 +363,8 @@ enum TBIAutoNegotiationAdvertisementRegister {
 };
 
 /* M5 control register */
-enum M5ControlRegister {
+enum M5ControlRegister
+{
      M5REG_RESERVED =   0xfffffffc,
      M5REG_RSS =        0x00000004,
      M5REG_RX_THREAD =  0x00000002,
@@ -368,7 +388,8 @@ struct ns_desc64
 };
 
 /* cmdsts flags for descriptors */
-enum CMDSTSFlatsForDescriptors {
+enum CMDSTSFlatsForDescriptors
+{
      CMDSTS_OWN =       0x80000000,
      CMDSTS_MORE =      0x40000000,
      CMDSTS_INTR =      0x20000000,
@@ -382,7 +403,8 @@ enum CMDSTSFlatsForDescriptors {
 };
 
 /* extended flags for descriptors */
-enum ExtendedFlagsForDescriptors {
+enum ExtendedFlagsForDescriptors
+{
      EXTSTS_UDPERR =    0x00400000,
      EXTSTS_UDPPKT =    0x00200000,
      EXTSTS_TCPERR =    0x00100000,

src/dev/net/sinic.hh

@@ -84,7 +84,8 @@ class Device : public Base
 {
   protected:
     /** Receive State Machine States */
-    enum RxState {
+    enum RxState
+    {
         rxIdle,
         rxFifoBlock,
         rxBeginCopy,
@@ -93,7 +94,8 @@ class Device : public Base
     };
 
     /** Transmit State Machine states */
-    enum TxState {
+    enum TxState
+    {
         txIdle,
         txFifoBlock,
         txBeginCopy,

src/dev/pci/copy_engine.hh

@@ -78,7 +78,8 @@ class CopyEngine : public PciDevice
 
         uint64_t completionDataReg;
 
-        enum ChannelState {
+        enum ChannelState
+        {
             Idle,
             AddressFetch,
             DescriptorFetch,

src/dev/ps2/touchkit.hh

@@ -46,12 +46,14 @@ struct PS2TouchKitParams;
 class PS2TouchKit : public PS2Device, public VncMouse
 {
   protected:
-    enum PS2Commands {
+    enum PS2Commands
+    {
         TpReadId = 0xE1,
         TouchKitDiag = 0x0A,
     };
 
-    enum TKCommands {
+    enum TKCommands
+    {
         TouchKitActive = 'A',
         TouchKitFWRev = 'D',
         TouchKitCtrlType = 'E',

src/dev/reg_bank.test.cc

@@ -896,7 +896,8 @@ class RegisterBankTest : public testing::Test
         {}
     };
 
-    enum AccessType {
+    enum AccessType
+    {
         Read,
         Write,
         PartialRead,

src/dev/serial/uart8250.hh

@@ -80,7 +80,8 @@ class Uart8250 : public Uart
         Bitfield<7> unused;
     EndBitUnion(Lsr)
 
-    enum class InterruptIds {
+    enum class InterruptIds
+    {
         Modem = 0, // Modem Status (lowest priority).
         Tx = 1,    // Tx Data.
         Rx = 2,    // Rx Data.

src/dev/sparc/iob.hh

@@ -78,7 +78,8 @@ class Iob : public PioDevice
     Addr iobJBusSize;
     Tick pioDelay;
 
-    enum DeviceId {
+    enum DeviceId
+    {
         Interal = 0,
         Error = 1,
         SSI = 2,
@@ -104,7 +105,8 @@ class Iob : public PioDevice
         int source;
     };
 
-    enum Type {
+    enum Type
+    {
         Interrupt,
         Reset,
         Idle,

src/dev/storage/ide_ctrl.cc

@@ -56,7 +56,8 @@
 using std::string;
 
 // Bus master IDE registers
-enum BMIRegOffset {
+enum BMIRegOffset
+{
     BMICommand = 0x0,
     BMIStatus = 0x2,
     BMIDescTablePtr = 0x4

src/gpu-compute/gpu_command_processor.hh

@@ -65,7 +65,8 @@ class GPUCommandProcessor : public HSADevice
     void setShader(Shader *shader);
     Shader* shader();
 
-    enum AgentCmd {
+    enum AgentCmd
+    {
       Nop = 0,
       Steal = 1
     };

src/gpu-compute/misc.hh

@@ -47,7 +47,8 @@ typedef std::bitset<std::numeric_limits<unsigned long long>::digits>
     VectorMask;
 typedef std::shared_ptr<GPUDynInst> GPUDynInstPtr;
 
-enum InstMemoryHop : int {
+enum InstMemoryHop : int
+{
     Initiate = 0,
     CoalsrSend = 1,
     CoalsrRecv = 2,
@@ -56,7 +57,8 @@ enum InstMemoryHop : int {
     InstMemoryHopMax = 5
 };
 
-enum BlockMemoryHop : int {
+enum BlockMemoryHop : int
+{
     BlockSend = 0,
     BlockRecv = 1
 };

src/gpu-compute/schedule_stage.hh

@@ -70,7 +70,8 @@ class ScheduleStage
 
     // Stats related variables and methods
     const std::string& name() const { return _name; }
-    enum SchNonRdyType {
+    enum SchNonRdyType
+    {
         SCH_SCALAR_ALU_NRDY,
         SCH_VECTOR_ALU_NRDY,
         SCH_VECTOR_MEM_ISSUE_NRDY,
@@ -92,13 +93,15 @@ class ScheduleStage
         SCH_RDY,
         SCH_NRDY_CONDITIONS
     };
-    enum schopdnonrdytype_e {
+    enum schopdnonrdytype_e
+    {
         SCH_VRF_OPD_NRDY,
         SCH_SRF_OPD_NRDY,
         SCH_RF_OPD_NRDY,
         SCH_RF_OPD_NRDY_CONDITIONS
     };
-    enum schrfaccessnonrdytype_e {
+    enum schrfaccessnonrdytype_e
+    {
         SCH_VRF_RD_ACCESS_NRDY,
         SCH_VRF_WR_ACCESS_NRDY,
         SCH_SRF_RD_ACCESS_NRDY,

src/gpu-compute/scoreboard_check_stage.hh

@@ -60,7 +60,8 @@ struct ComputeUnitParams;
 class ScoreboardCheckStage
 {
   public:
-    enum nonrdytype_e {
+    enum nonrdytype_e
+    {
         NRDY_ILLEGAL,
         NRDY_WF_STOP,
         NRDY_IB_EMPTY,

src/gpu-compute/wavefront.hh

@@ -59,7 +59,8 @@
 class Wavefront : public SimObject
 {
   public:
-    enum status_e {
+    enum status_e
+    {
         // wavefront is stalled
         S_STOPPED,
         // wavefront is returning from a kernel

src/mem/cache/base.hh

@@ -92,7 +92,8 @@ class BaseCache : public ClockedObject
     /**
      * Indexes to enumerate the MSHR queues.
      */
-    enum MSHRQueueIndex {
+    enum MSHRQueueIndex
+    {
         MSHRQueue_MSHRs,
         MSHRQueue_WriteBuffer
     };
@@ -101,7 +102,8 @@ class BaseCache : public ClockedObject
     /**
      * Reasons for caches to be blocked.
      */
-    enum BlockedCause {
+    enum BlockedCause
+    {
         Blocked_NoMSHRs = MSHRQueue_MSHRs,
         Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
         Blocked_NoTargets,
@@ -1447,7 +1449,8 @@ class WriteAllocator : public SimObject
      * normal operation (ALLOCATE), write coalescing (COALESCE), or
      * write coalescing without allocation (NO_ALLOCATE).
      */
-    enum class WriteMode : char {
+    enum class WriteMode : char
+    {
         ALLOCATE,
         COALESCE,
         NO_ALLOCATE,

src/mem/cache/mshr.hh

@@ -125,7 +125,8 @@ class MSHR : public QueueEntry, public Printable
     {
       public:
 
-        enum Source {
+        enum Source
+        {
             FromCPU,
             FromSnoop,
             FromPrefetcher

src/mem/cache/prefetch/bop.hh

@@ -49,7 +49,8 @@ class BOP : public Queued
 {
     private:
 
-        enum RRWay {
+        enum RRWay
+        {
             Left,
             Right
         };

src/mem/page_table.hh

@@ -89,7 +89,8 @@ class EmulationPageTable : public Serializable
      * bit 2 - cacheable  | uncacheable
      * bit 3 - read-write | read-only
      */
-    enum MappingFlags : uint32_t {
+    enum MappingFlags : uint32_t
+    {
         Clobber     = 1,
         Uncacheable = 4,
         ReadOnly    = 8,

src/mem/request.hh

@@ -72,7 +72,8 @@
  */
 
 namespace ContextSwitchTaskId {
-    enum TaskId {
+    enum TaskId
+    {
         MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
         Prefetcher = 1022, /* For cache lines brought in by prefetcher */
         DMA = 1023, /* Mostly Table Walker */

src/mem/se_translating_port_proxy.hh

@@ -47,7 +47,8 @@ class SETranslatingPortProxy : public TranslatingPortProxy
 {
 
   public:
-    enum AllocType {
+    enum AllocType
+    {
         Always,
         Never,
         NextPage

src/mem/snoop_filter.hh

@@ -308,7 +308,8 @@ class SnoopFilter : public SimObject
     /**
      * Use the lower bits of the address to keep track of the line status
      */
-    enum LineStatus {
+    enum LineStatus
+    {
         /** block holds data from the secure memory space */
         LineSecure = 0x01,
     };

src/proto/inst.proto

@@ -61,7 +61,8 @@ message Inst {
   optional uint32 cpuid = 4;
   optional fixed64 tick = 5;
 
-  enum InstType {
+  enum InstType
+  {
     None = 0;
     IntAlu = 1;
     IntMul = 2;

src/proto/inst_dep_record.proto

@@ -61,7 +61,8 @@ message InstDepRecordHeader {
 // occupancy during replay. An optional field is provided for the instruction
 // PC.
 message InstDepRecord {
-  enum RecordType {
+  enum RecordType
+  {
     INVALID = 0;
     LOAD = 1;
     STORE = 2;

src/python/m5/params.py

@@ -1328,7 +1328,8 @@ class MetaEnum(MetaParamValue):
 ''')
         if cls.is_class:
             code('''\
-enum class $name {
+enum class $name
+{
 ''')
         else:
             code('''\

src/sim/aux_vector.hh

@@ -54,7 +54,8 @@ swap_byte(AuxVector<IntType> av)
     return av;
 }
 
-enum AuxiliaryVectorType {
+enum AuxiliaryVectorType
+{
     M5_AT_NULL = 0,        // End of vector.
     M5_AT_IGNORE = 1,      // Ignored.
     M5_AT_EXECFD = 2,      // File descriptor of program if interpreter used.