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misc: Fix coding style for struct's opening braces

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The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-01-09 12:28:03 -03:00
committed by Daniel Carvalho
parent f96de41fcf
commit 2922f763e1
109 changed files with 584 additions and 292 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/arch/arm/freebsd/freebsd.hh
View File

@@ -86,19 +86,22 @@ class ArmFreebsd32 : public ArmFreebsd
static const unsigned TGT_MAP_FIXED = 0x0010;
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint32_t rlim_cur; //!< soft limit
uint32_t rlim_max; //!< hard limit
};
/// For gettimeofday().
struct timeval {
struct timeval
{
int32_t tv_sec; //!< seconds
int32_t tv_usec; //!< microseconds
};
// For writev/readv
struct tgt_iovec {
struct tgt_iovec
{
uint32_t iov_base; // void *
uint32_t iov_len;
};
@@ -170,7 +173,8 @@ class ArmFreebsd32 : public ArmFreebsd
} tgt_stat64;
/// For getrusage().
struct rusage {
struct rusage
{
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int32_t ru_maxrss; //!< max rss
@@ -190,7 +194,8 @@ class ArmFreebsd32 : public ArmFreebsd
};
/// For times().
struct tms {
struct tms
{
int32_t tms_utime; //!< user time
int32_t tms_stime; //!< system time
int32_t tms_cutime; //!< user time of children
@@ -269,19 +274,22 @@ class ArmFreebsd64 : public ArmFreebsd
};
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint64_t rlim_cur; //!< soft limit
uint64_t rlim_max; //!< hard limit
};
/// For gettimeofday().
struct timeval {
struct timeval
{
int64_t tv_sec; //!< seconds
int64_t tv_usec; //!< microseconds
};
// For writev/readv
struct tgt_iovec {
struct tgt_iovec
{
uint64_t iov_base; // void *
uint64_t iov_len;
};
@@ -335,7 +343,8 @@ class ArmFreebsd64 : public ArmFreebsd
} tgt_stat64;
/// For getrusage().
struct rusage {
struct rusage
{
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int64_t ru_maxrss; //!< max rss
@@ -355,7 +364,8 @@ class ArmFreebsd64 : public ArmFreebsd
};
/// For times().
struct tms {
struct tms
{
int64_t tms_utime; //!< user time
int64_t tms_stime; //!< system time
int64_t tms_cutime; //!< user time of children

3
src/arch/arm/insts/neon64_mem.hh
View File

@@ -47,7 +47,8 @@ namespace ArmISA
typedef uint64_t XReg;
/// 128-bit NEON vector register.
struct VReg {
struct VReg
{
XReg hi;
XReg lo;
};

3
src/arch/arm/isa.hh
View File

@@ -112,7 +112,8 @@ namespace ArmISA
SelfDebug * selfDebug;
/** MiscReg metadata **/
struct MiscRegLUTEntry {
struct MiscRegLUTEntry
{
uint32_t lower; // Lower half mapped to this register
uint32_t upper; // Upper half mapped to this register
uint64_t _reset; // value taken on reset (i.e. initialization)

6
src/arch/arm/kvm/arm_cpu.hh
View File

@@ -67,7 +67,8 @@ class ArmKvmCPU : public BaseKvmCPU
void dump();
protected:
struct KvmIntRegInfo {
struct KvmIntRegInfo
{
/** KVM ID */
const uint64_t id;
/** gem5 index */
@@ -76,7 +77,8 @@ class ArmKvmCPU : public BaseKvmCPU
const char *name;
};
struct KvmCoreMiscRegInfo {
struct KvmCoreMiscRegInfo
{
/** KVM ID */
const uint64_t id;
/** gem5 index */

6
src/arch/arm/kvm/armv8_cpu.hh
View File

@@ -92,7 +92,8 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
protected:
/** Mapping between integer registers in gem5 and KVM */
struct IntRegInfo {
struct IntRegInfo
{
IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char *_name)
: kvm(_kvm), idx(_idx), name(_name) {}
@@ -105,7 +106,8 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
};
/** Mapping between misc registers in gem5 and registers in KVM */
struct MiscRegInfo {
struct MiscRegInfo
{
MiscRegInfo(uint64_t _kvm, ArmISA::MiscRegIndex _idx,
const char *_name, bool _is_device = false)
: kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {}

33
src/arch/arm/linux/atag.hh
View File

@@ -195,23 +195,27 @@ class AtagNone : public AtagHeader
#define ATAG_CMDLINE 0x54410009
// structures for each atag
struct atag_header {
struct atag_header
{
u32 size; // length of tag in words including this header
u32 tag; // tag type
};
struct atag_core {
struct atag_core
{
u32 flags;
u32 pagesize;
u32 rootdev;
};
struct atag_mem {
struct atag_mem
{
u32 size;
u32 start;
};
struct atag_videotext {
struct atag_videotext
{
u8 x;
u8 y;
u16 video_page;
@@ -223,27 +227,32 @@ struct atag_videotext {
u16 video_points;
};
struct atag_ramdisk {
struct atag_ramdisk
{
u32 flags;
u32 size;
u32 start;
};
struct atag_initrd2 {
struct atag_initrd2
{
u32 start;
u32 size;
};
struct atag_serialnr {
struct atag_serialnr
{
u32 low;
u32 high;
};
struct atag_revision {
struct atag_revision
{
u32 rev;
};
struct atag_videolfb {
struct atag_videolfb
{
u16 lfb_width;
u16 lfb_height;
u16 lfb_depth;
@@ -260,11 +269,13 @@ struct atag_videolfb {
u8 rsvd_pos;
};
struct atag_cmdline {
struct atag_cmdline
{
char cmdline[1];
};
struct atag {
struct atag
{
struct atag_header hdr;
union {
struct atag_core core;

36
src/arch/arm/linux/linux.hh
View File

@@ -166,24 +166,28 @@ class ArmLinux32 : public ArmLinux
static const int TBL_SYSINFO = 12;
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint32_t rlim_cur; //!< soft limit
uint32_t rlim_max; //!< hard limit
};
/// For gettimeofday().
struct timeval {
struct timeval
{
int32_t tv_sec; //!< seconds
int32_t tv_usec; //!< microseconds
};
struct timespec {
struct timespec
{
int32_t tv_sec; //!< seconds
int32_t tv_nsec; //!< nanoseconds
};
// For writev/readv
struct tgt_iovec {
struct tgt_iovec
{
uint32_t iov_base; // void *
uint32_t iov_len;
};
@@ -248,7 +252,8 @@ class ArmLinux32 : public ArmLinux
} tgt_sysinfo;
/// For getrusage().
struct rusage {
struct rusage
{
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int32_t ru_maxrss; //!< max rss
@@ -268,7 +273,8 @@ class ArmLinux32 : public ArmLinux
};
/// For times().
struct tms {
struct tms
{
int32_t tms_utime; //!< user time
int32_t tms_stime; //!< system time
int32_t tms_cutime; //!< user time of children
@@ -426,24 +432,28 @@ class ArmLinux64 : public ArmLinux
};
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint64_t rlim_cur; //!< soft limit
uint64_t rlim_max; //!< hard limit
};
/// For gettimeofday().
struct timeval {
struct timeval
{
int64_t tv_sec; //!< seconds
int64_t tv_usec; //!< microseconds
};
struct timespec {
struct timespec
{
int64_t tv_sec; //!< seconds
int64_t tv_nsec; //!< nanoseconds
};
// For writev/readv
struct tgt_iovec {
struct tgt_iovec
{
uint64_t iov_base; // void *
uint64_t iov_len;
};
@@ -505,7 +515,8 @@ class ArmLinux64 : public ArmLinux
} tgt_sysinfo;
/// For getrusage().
struct rusage {
struct rusage
{
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int64_t ru_maxrss; //!< max rss
@@ -525,7 +536,8 @@ class ArmLinux64 : public ArmLinux
};
/// For times().
struct tms {
struct tms
{
int64_t tms_utime; //!< user time
int64_t tms_stime; //!< system time
int64_t tms_cutime; //!< user time of children

3
src/arch/arm/nativetrace.hh
View File

@@ -70,7 +70,8 @@ class ArmNativeTrace : public NativeTrace
};
protected:
struct ThreadState {
struct ThreadState
{
bool changed[STATE_NUMVALS];
uint64_t state[2][STATE_NUMVALS];
uint64_t *newState;

9
src/arch/arm/pmu.hh
View File

@@ -290,7 +290,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice
/**
* Event definition base class
*/
struct PMUEvent {
struct PMUEvent
{
PMUEvent() {}
@@ -341,7 +342,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice
std::set<PMU::CounterState*> userCounters;
};
struct RegularEvent : public PMUEvent {
struct RegularEvent : public PMUEvent
{
typedef std::pair<SimObject*, std::string> EventTypeEntry;
void addMicroarchitectureProbe(SimObject* object,
@@ -407,7 +409,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice
PMUEvent* getEvent(uint64_t eventId);
/** State of a counter within the PMU. **/
struct CounterState : public Serializable {
struct CounterState : public Serializable
{
CounterState(PMU &pmuReference, uint64_t counter_id)
: eventId(0), filter(0), enabled(false),
overflow64(false), sourceEvent(nullptr),

6
src/arch/arm/remote_gdb.hh
View File

@@ -66,7 +66,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct M5_ATTR_PACKED {
struct M5_ATTR_PACKED
{
uint32_t gpr[16];
uint32_t cpsr;
uint64_t fpr[32];
@@ -88,7 +89,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct M5_ATTR_PACKED {
struct M5_ATTR_PACKED
{
uint64_t x[31];
uint64_t spx;
uint64_t pc;

3
src/arch/arm/table_walker.cc
View File

@@ -1011,7 +1011,8 @@ TableWalker::processWalkAArch64()
// (grain_size + N*stride), for N = {1, 2, 3}.
// A value of 64 will never succeed and a value of 0 will always succeed.
if (start_lookup_level == MAX_LOOKUP_LEVELS) {
struct GrainMap {
struct GrainMap
{
GrainSize grain_size;
unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS];
};

3
src/arch/arm/table_walker.hh
View File

@@ -894,7 +894,8 @@ class TableWalker : public ClockedObject
bool _haveLargeAsid64;
/** Statistics */
struct TableWalkerStats : public Stats::Group {
struct TableWalkerStats : public Stats::Group
{
TableWalkerStats(Stats::Group *parent);
Stats::Scalar walks;
Stats::Scalar walksShortDescriptor;

87
src/arch/gcn3/gpu_decoder.hh
View File

@@ -1351,7 +1351,8 @@ namespace Gcn3ISA
GPUStaticInst* decode_invalid(MachInst);
};
struct InFmt_DS {
struct InFmt_DS
{
unsigned int OFFSET0 : 8;
unsigned int OFFSET1 : 8;
unsigned int GDS : 1;
@@ -1360,14 +1361,16 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_DS_1 {
struct InFmt_DS_1
{
unsigned int ADDR : 8;
unsigned int DATA0 : 8;
unsigned int DATA1 : 8;
unsigned int VDST : 8;
};
struct InFmt_EXP {
struct InFmt_EXP
{
unsigned int EN : 4;
unsigned int TGT : 6;
unsigned int COMPR : 1;
@@ -1377,14 +1380,16 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_EXP_1 {
struct InFmt_EXP_1
{
unsigned int VSRC0 : 8;
unsigned int VSRC1 : 8;
unsigned int VSRC2 : 8;
unsigned int VSRC3 : 8;
};
struct InFmt_FLAT {
struct InFmt_FLAT
{
unsigned int pad_0_15 : 16;
unsigned int GLC : 1;
unsigned int SLC : 1;
@@ -1393,7 +1398,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_FLAT_1 {
struct InFmt_FLAT_1
{
unsigned int ADDR : 8;
unsigned int DATA : 8;
unsigned int pad_16_22 : 7;
@@ -1401,11 +1407,13 @@ namespace Gcn3ISA
unsigned int VDST : 8;
};
struct InFmt_INST {
struct InFmt_INST
{
unsigned int ENCODING : 32;
};
struct InFmt_MIMG {
struct InFmt_MIMG
{
unsigned int pad_0_7 : 8;
unsigned int DMASK : 4;
unsigned int UNORM : 1;
@@ -1419,7 +1427,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_MIMG_1 {
struct InFmt_MIMG_1
{
unsigned int VADDR : 8;
unsigned int VDATA : 8;
unsigned int SRSRC : 5;
@@ -1428,7 +1437,8 @@ namespace Gcn3ISA
unsigned int D16 : 1;
};
struct InFmt_MTBUF {
struct InFmt_MTBUF
{
unsigned int OFFSET : 12;
unsigned int OFFEN : 1;
unsigned int IDXEN : 1;
@@ -1439,7 +1449,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_MTBUF_1 {
struct InFmt_MTBUF_1
{
unsigned int VADDR : 8;
unsigned int VDATA : 8;
unsigned int SRSRC : 5;
@@ -1449,7 +1460,8 @@ namespace Gcn3ISA
unsigned int SOFFSET : 8;
};
struct InFmt_MUBUF {
struct InFmt_MUBUF
{
unsigned int OFFSET : 12;
unsigned int OFFEN : 1;
unsigned int IDXEN : 1;
@@ -1462,7 +1474,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_MUBUF_1 {
struct InFmt_MUBUF_1
{
unsigned int VADDR : 8;
unsigned int VDATA : 8;
unsigned int SRSRC : 5;
@@ -1471,7 +1484,8 @@ namespace Gcn3ISA
unsigned int SOFFSET : 8;
};
struct InFmt_SMEM {
struct InFmt_SMEM
{
unsigned int SBASE : 6;
unsigned int SDATA : 7;
unsigned int pad_13_15 : 3;
@@ -1481,18 +1495,21 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_SMEM_1 {
struct InFmt_SMEM_1
{
unsigned int OFFSET : 20;
};
struct InFmt_SOP1 {
struct InFmt_SOP1
{
unsigned int SSRC0 : 8;
unsigned int OP : 8;
unsigned int SDST : 7;
unsigned int ENCODING : 9;
};
struct InFmt_SOP2 {
struct InFmt_SOP2
{
unsigned int SSRC0 : 8;
unsigned int SSRC1 : 8;
unsigned int SDST : 7;
@@ -1500,27 +1517,31 @@ namespace Gcn3ISA
unsigned int ENCODING : 2;
};
struct InFmt_SOPC {
struct InFmt_SOPC
{
unsigned int SSRC0 : 8;
unsigned int SSRC1 : 8;
unsigned int OP : 7;
unsigned int ENCODING : 9;
};
struct InFmt_SOPK {
struct InFmt_SOPK
{
unsigned int SIMM16 : 16;
unsigned int SDST : 7;
unsigned int OP : 5;
unsigned int ENCODING : 4;
};
struct InFmt_SOPP {
struct InFmt_SOPP
{
unsigned int SIMM16 : 16;
unsigned int OP : 7;
unsigned int ENCODING : 9;
};
struct InFmt_VINTRP {
struct InFmt_VINTRP
{
unsigned int VSRC : 8;
unsigned int ATTRCHAN : 2;
unsigned int ATTR : 6;
@@ -1529,14 +1550,16 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_VOP1 {
struct InFmt_VOP1
{
unsigned int SRC0 : 9;
unsigned int OP : 8;
unsigned int VDST : 8;
unsigned int ENCODING : 7;
};
struct InFmt_VOP2 {
struct InFmt_VOP2
{
unsigned int SRC0 : 9;
unsigned int VSRC1 : 8;
unsigned int VDST : 8;
@@ -1544,7 +1567,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 1;
};
struct InFmt_VOP3 {
struct InFmt_VOP3
{
unsigned int VDST : 8;
unsigned int ABS : 3;
unsigned int pad_11_14 : 4;
@@ -1553,7 +1577,8 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_VOP3_1 {
struct InFmt_VOP3_1
{
unsigned int SRC0 : 9;
unsigned int SRC1 : 9;
unsigned int SRC2 : 9;
@@ -1561,7 +1586,8 @@ namespace Gcn3ISA
unsigned int NEG : 3;
};
struct InFmt_VOP3_SDST_ENC {
struct InFmt_VOP3_SDST_ENC
{
unsigned int VDST : 8;
unsigned int SDST : 7;
unsigned int CLAMP : 1;
@@ -1569,14 +1595,16 @@ namespace Gcn3ISA
unsigned int ENCODING : 6;
};
struct InFmt_VOPC {
struct InFmt_VOPC
{
unsigned int SRC0 : 9;
unsigned int VSRC1 : 8;
unsigned int OP : 8;
unsigned int ENCODING : 7;
};
struct InFmt_VOP_DPP {
struct InFmt_VOP_DPP
{
unsigned int SRC0 : 8;
unsigned int DPP_CTRL : 9;
unsigned int pad_17_18 : 2;
@@ -1589,7 +1617,8 @@ namespace Gcn3ISA
unsigned int ROW_MASK : 4;
};
struct InFmt_VOP_SDWA {
struct InFmt_VOP_SDWA
{
unsigned int SRC0 : 8;
unsigned int DST_SEL : 3;
unsigned int DST_UNUSED : 2;

3
src/arch/mips/linux/hwrpb.hh
View File

@@ -28,7 +28,8 @@
#include "arch/mips/linux/aligned.hh"
namespace Linux {
struct pcb_struct {
struct pcb_struct
{
uint64_ta rpb_ksp;
uint64_ta rpb_usp;
uint64_ta rpb_ptbr;

3
src/arch/mips/linux/thread_info.hh
View File

@@ -32,7 +32,8 @@
#include "arch/mips/linux/hwrpb.hh"
namespace Linux {
struct thread_info {
struct thread_info
{
struct pcb_struct pcb;
Addr_a task;
};

3
src/arch/mips/types.hh
View File

@@ -72,7 +72,8 @@ enum RoundMode{
RND_NEAREST
};
struct CoreSpecific {
struct CoreSpecific
{
CoreSpecific()
: CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),

3
src/arch/power/linux/linux.hh
View File

@@ -91,7 +91,8 @@ class PowerLinux : public Linux
} tgt_stat64;
/// For times().
struct tms {
struct tms
{
int32_t tms_utime; //!< user time
int32_t tms_stime; //!< system time
int32_t tms_cutime; //!< user time of children

3
src/arch/power/types.hh
View File

@@ -89,7 +89,8 @@ typedef GenericISA::SimplePCState<MachInst> PCState;
namespace std {
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t>
{
size_t operator()(const PowerISA::ExtMachInst &emi) const {
return hash<uint32_t>::operator()((uint32_t)emi);
};

9
src/arch/riscv/linux/linux.hh
View File

@@ -132,7 +132,8 @@ class RiscvLinux64 : public RiscvLinux
typedef uint64_t blksize_t;
typedef uint64_t blkcnt_t;
struct timespec {
struct timespec
{
time_t tv_sec;
int64_t tv_nsec;
};
@@ -297,12 +298,14 @@ class RiscvLinux32 : public RiscvLinux
typedef int64_t time_t;
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint32_t rlim_cur; //!< soft limit
uint32_t rlim_max; //!< hard limit
};
struct timespec {
struct timespec
{
time_t tv_sec;
int32_t tv_nsec;
};

3
src/arch/x86/linux/syscalls.hh
View File

@@ -51,7 +51,8 @@ BitUnion32(UserDescFlags)
Bitfield<6> useable;
EndBitUnion(UserDescFlags)
struct UserDesc32 {
struct UserDesc32
{
uint32_t entry_number;
uint32_t base_addr;
uint32_t limit;

3
src/arch/x86/nativetrace.hh
View File

@@ -44,7 +44,8 @@ class X86NativeTrace : public NativeTrace
uint64_t oldRcxVal, oldR11Val;
uint64_t oldRealRcxVal, oldRealR11Val;
struct ThreadState {
struct ThreadState
{
uint64_t rax;
uint64_t rcx;
uint64_t rdx;

3
src/arch/x86/process.cc
View File

@@ -279,7 +279,8 @@ X86_64Process::initState()
TSShigh TSSDescHigh = 0;
TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
struct TSSDesc {
struct TSSDesc
{
uint64_t low;
uint64_t high;
} tssDescVal = {TSSDescLow, TSSDescHigh};

3
src/arch/x86/remote_gdb.hh
View File

@@ -93,7 +93,8 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct M5_ATTR_PACKED {
struct M5_ATTR_PACKED
{
uint64_t rax;
uint64_t rbx;
uint64_t rcx;

3
src/arch/x86/tlb.hh
View File

@@ -101,7 +101,8 @@ namespace X86ISA
AddrRange m5opRange;
struct TlbStats : public Stats::Group {
struct TlbStats : public Stats::Group
{
TlbStats(Stats::Group *parent);
Stats::Scalar rdAccesses;

9
src/base/bmpwriter.hh
View File

@@ -75,7 +75,8 @@ class BmpWriter : public ImgWriter
void write(std::ostream &bmp) const override;
private:
struct M5_ATTR_PACKED FileHeader {
struct M5_ATTR_PACKED FileHeader
{
unsigned char magic_number[2];
uint32_t size;
uint16_t reserved1;
@@ -97,12 +98,14 @@ class BmpWriter : public ImgWriter
uint32_t ClrImportant;
};
struct M5_ATTR_PACKED CompleteV1Header {
struct M5_ATTR_PACKED CompleteV1Header
{
FileHeader file;
InfoHeaderV1 info;
};
struct M5_ATTR_PACKED BmpPixel32 {
struct M5_ATTR_PACKED BmpPixel32
{
BmpPixel32 &operator=(const Pixel &rhs) {
red = rhs.red;
green = rhs.green;

9
src/base/inet.hh
View File

@@ -550,12 +550,14 @@ class Ip6Ptr
// Dnet supplied ipv6 opt header is incomplete and
// newer NIC card filters expect a more robust
// ipv6 header option declaration.
struct ip6_opt_fragment {
struct ip6_opt_fragment
{
uint16_t offlg;
uint32_t ident;
};
struct ip6_opt_routing_type2 {
struct ip6_opt_routing_type2
{
uint8_t type;
uint8_t segleft;
uint32_t reserved;
@@ -563,7 +565,8 @@ struct ip6_opt_routing_type2 {
};
#define HOME_ADDRESS_OPTION 0xC9
struct M5_ATTR_PACKED ip6_opt_dstopts {
struct M5_ATTR_PACKED ip6_opt_dstopts
{
uint8_t type;
uint8_t length;
ip6_addr_t addr;

3
src/base/pixel.hh
View File

@@ -91,7 +91,8 @@ class PixelConverter
/**
* Color channel conversion and scaling helper class.
*/
struct Channel {
struct Channel
{
/**
* @param offset Offset in bits.
* @param width Width in bits.

3
src/base/pngwriter.cc
View File

@@ -73,7 +73,8 @@ writePng(png_structp pngPtr, png_bytep data, png_size_t length)
strmPtr->write(reinterpret_cast<const char *>(data), length);
}
struct PngWriter::PngStructHandle {
struct PngWriter::PngStructHandle
{
private:
// Make PngStructHandle uncopyable
PngStructHandle(const PngStructHandle&) = delete;

3
src/base/pngwriter.hh
View File

@@ -76,7 +76,8 @@ class PngWriter : public ImgWriter
void write(std::ostream &png) const override;
private:
/** Png Pixel type: not containing padding */
struct M5_ATTR_PACKED PngPixel24 {
struct M5_ATTR_PACKED PngPixel24
{
PngPixel24 &operator=(const Pixel &rhs) {
red = rhs.red;
green = rhs.green;

21
src/base/vnc/vncinput.hh
View File

@@ -96,7 +96,8 @@ class VncInput : public SimObject
ClientCutText = 6
};
struct M5_ATTR_PACKED PixelFormat {
struct M5_ATTR_PACKED PixelFormat
{
uint8_t bpp;
uint8_t depth;
uint8_t bigendian;
@@ -110,19 +111,22 @@ class VncInput : public SimObject
uint8_t padding[3];
};
struct M5_ATTR_PACKED PixelFormatMessage {
struct M5_ATTR_PACKED PixelFormatMessage
{
uint8_t type;
uint8_t padding[3];
PixelFormat px;
};
struct M5_ATTR_PACKED PixelEncodingsMessage {
struct M5_ATTR_PACKED PixelEncodingsMessage
{
uint8_t type;
uint8_t padding;
uint16_t num_encodings;
};
struct M5_ATTR_PACKED FrameBufferUpdateReq {
struct M5_ATTR_PACKED FrameBufferUpdateReq
{
uint8_t type;
uint8_t incremental;
uint16_t x;
@@ -131,21 +135,24 @@ class VncInput : public SimObject
uint16_t height;
};
struct M5_ATTR_PACKED KeyEventMessage {
struct M5_ATTR_PACKED KeyEventMessage
{
uint8_t type;
uint8_t down_flag;
uint8_t padding[2];
uint32_t key;
};
struct M5_ATTR_PACKED PointerEventMessage {
struct M5_ATTR_PACKED PointerEventMessage
{
uint8_t type;
uint8_t button_mask;
uint16_t x;
uint16_t y;
};
struct M5_ATTR_PACKED ClientCutTextMessage {
struct M5_ATTR_PACKED ClientCutTextMessage
{
uint8_t type;
uint8_t padding[3];
uint32_t length;

12
src/base/vnc/vncserver.hh
View File

@@ -106,7 +106,8 @@ class VncServer : public VncInput
NormalPhase
};
struct M5_ATTR_PACKED ServerInitMsg {
struct M5_ATTR_PACKED ServerInitMsg
{
uint16_t fbWidth;
uint16_t fbHeight;
PixelFormat px;
@@ -114,13 +115,15 @@ class VncServer : public VncInput
char name[2]; // just to put M5 in here
};
struct M5_ATTR_PACKED FrameBufferUpdate {
struct M5_ATTR_PACKED FrameBufferUpdate
{
uint8_t type;
uint8_t padding;
uint16_t num_rects;
};
struct M5_ATTR_PACKED FrameBufferRect {
struct M5_ATTR_PACKED FrameBufferRect
{
uint16_t x;
uint16_t y;
uint16_t width;
@@ -128,7 +131,8 @@ class VncServer : public VncInput
int32_t encoding;
};
struct M5_ATTR_PACKED ServerCutText {
struct M5_ATTR_PACKED ServerCutText
{
uint8_t type;
uint8_t padding[3];
uint32_t length;

3
src/cpu/base.hh
View File

@@ -146,7 +146,8 @@ class BaseCPU : public ClockedObject
const unsigned int _cacheLineSize;
/** Global CPU statistics that are merged into the Root object. */
struct GlobalStats : public Stats::Group {
struct GlobalStats : public Stats::Group
{
GlobalStats(::Stats::Group *parent);
::Stats::Value simInsts;

3
src/cpu/kvm/base.hh
View File

@@ -780,7 +780,8 @@ class BaseKvmCPU : public BaseCPU
public:
/* @{ */
struct StatGroup : public Stats::Group {
struct StatGroup : public Stats::Group
{
StatGroup(Stats::Group *parent);
Stats::Scalar committedInsts;
Stats::Scalar numVMExits;

9
src/cpu/kvm/device.cc
View File

@@ -60,7 +60,8 @@ void
KvmDevice::getAttrPtr(uint32_t group, uint64_t attr, void *data) const
{
#ifdef KVM_GET_DEVICE_ATTR
struct kvm_device_attr dattr = {
struct kvm_device_attr dattr =
{
0, // Flags
group,
attr,
@@ -80,7 +81,8 @@ void
KvmDevice::setAttrPtr(uint32_t group, uint64_t attr, const void *data) const
{
#ifdef KVM_SET_DEVICE_ATTR
struct kvm_device_attr dattr = {
struct kvm_device_attr dattr =
{
0, // Flags
group,
attr,
@@ -100,7 +102,8 @@ bool
KvmDevice::hasAttr(uint32_t group, uint64_t attr) const
{
#ifdef KVM_HAS_DEVICE_ATTR
struct kvm_device_attr dattr = {
struct kvm_device_attr dattr =
{
0, // Flags
group,
attr,

3
src/cpu/minor/decode.hh
View File

@@ -88,7 +88,8 @@ class Decode : public Named
protected:
/** Data members after this line are cycle-to-cycle state */
struct DecodeThreadInfo {
struct DecodeThreadInfo
{
/** Default Constructor */
DecodeThreadInfo() :

3
src/cpu/minor/execute.hh
View File

@@ -145,7 +145,8 @@ class Execute : public Named
DrainAllInsts /* Discarding all remaining insts */
};
struct ExecuteThreadInfo {
struct ExecuteThreadInfo
{
/** Constructor */
ExecuteThreadInfo(unsigned int insts_committed) :
inputIndex(0),

3
src/cpu/minor/fetch1.hh
View File

@@ -236,7 +236,8 @@ class Fetch1 : public Named
/** Stage cycle-by-cycle state */
struct Fetch1ThreadInfo {
struct Fetch1ThreadInfo
{
/** Consturctor to initialize all fields. */
Fetch1ThreadInfo() :

3
src/cpu/minor/fetch2.hh
View File

@@ -98,7 +98,8 @@ class Fetch2 : public Named
protected:
/** Data members after this line are cycle-to-cycle state */
struct Fetch2ThreadInfo {
struct Fetch2ThreadInfo
{
/** Default constructor */
Fetch2ThreadInfo() :

30
src/cpu/o3/comm.hh
View File

@@ -51,7 +51,8 @@
/** Struct that defines the information passed from fetch to decode. */
template<class Impl>
struct DefaultFetchDefaultDecode {
struct DefaultFetchDefaultDecode
{
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -64,7 +65,8 @@ struct DefaultFetchDefaultDecode {
/** Struct that defines the information passed from decode to rename. */
template<class Impl>
struct DefaultDecodeDefaultRename {
struct DefaultDecodeDefaultRename
{
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -74,7 +76,8 @@ struct DefaultDecodeDefaultRename {
/** Struct that defines the information passed from rename to IEW. */
template<class Impl>
struct DefaultRenameDefaultIEW {
struct DefaultRenameDefaultIEW
{
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -84,7 +87,8 @@ struct DefaultRenameDefaultIEW {
/** Struct that defines the information passed from IEW to commit. */
template<class Impl>
struct DefaultIEWDefaultCommit {
struct DefaultIEWDefaultCommit
{
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -102,7 +106,8 @@ struct DefaultIEWDefaultCommit {
};
template<class Impl>
struct IssueStruct {
struct IssueStruct
{
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -112,9 +117,11 @@ struct IssueStruct {
/** Struct that defines all backwards communication. */
template<class Impl>
struct TimeBufStruct {
struct TimeBufStruct
{
typedef typename Impl::DynInstPtr DynInstPtr;
struct decodeComm {
struct decodeComm
{
TheISA::PCState nextPC;
DynInstPtr mispredictInst;
DynInstPtr squashInst;
@@ -130,12 +137,14 @@ struct TimeBufStruct {
decodeComm decodeInfo[Impl::MaxThreads];
struct renameComm {
struct renameComm
{
};
renameComm renameInfo[Impl::MaxThreads];
struct iewComm {
struct iewComm
{
// Also eventually include skid buffer space.
unsigned freeIQEntries;
unsigned freeLQEntries;
@@ -153,7 +162,8 @@ struct TimeBufStruct {
iewComm iewInfo[Impl::MaxThreads];
struct commitComm {
struct commitComm
{
/////////////////////////////////////////////////////////////////////
// This code has been re-structured for better packing of variables
// instead of by stage which is the more logical way to arrange the

3
src/cpu/o3/commit.hh
View File

@@ -480,7 +480,8 @@ class DefaultCommit
int htmStarts[Impl::MaxThreads];
int htmStops[Impl::MaxThreads];
struct CommitStats : public Stats::Group {
struct CommitStats : public Stats::Group
{
CommitStats(O3CPU *cpu, DefaultCommit *commit);
/** Stat for the total number of squashed instructions discarded by
* commit.

6
src/cpu/o3/decode.hh
View File

@@ -246,7 +246,8 @@ class DefaultDecode
bool wroteToTimeBuffer;
/** Source of possible stalls. */
struct Stalls {
struct Stalls
{
bool rename;
};
@@ -292,7 +293,8 @@ class DefaultDecode
*/
bool squashAfterDelaySlot[Impl::MaxThreads];
struct DecodeStats : public Stats::Group {
struct DecodeStats : public Stats::Group
{
DecodeStats(O3CPU *cpu);
/** Stat for total number of idle cycles. */

3
src/cpu/o3/fetch.hh
View File

@@ -449,7 +449,8 @@ class DefaultFetch
int numInst;
/** Source of possible stalls. */
struct Stalls {
struct Stalls
{
bool decode;
bool drain;
};

6
src/cpu/o3/inst_queue.hh
View File

@@ -332,7 +332,8 @@ class InstructionQueue
* numbers (and hence are older) will be at the top of the
* priority queue.
*/
struct pqCompare {
struct pqCompare
{
bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
{
return lhs->seqNum > rhs->seqNum;
@@ -359,7 +360,8 @@ class InstructionQueue
typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
/** Entry for the list age ordering by op class. */
struct ListOrderEntry {
struct ListOrderEntry
{
OpClass queueType;
InstSeqNum oldestInst;
};

3
src/cpu/o3/mem_dep_unit.hh
View File

@@ -51,7 +51,8 @@
#include "cpu/inst_seq.hh"
#include "debug/MemDepUnit.hh"
struct SNHash {
struct SNHash
{
size_t operator() (const InstSeqNum &seq_num) const {
unsigned a = (unsigned)seq_num;
unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;

3
src/cpu/o3/probe/elastic_trace.hh
View File

@@ -504,7 +504,8 @@ class ElasticTrace : public ProbeListenerObject
*/
bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
struct ElasticTraceStats : public Stats::Group {
struct ElasticTraceStats : public Stats::Group
{
ElasticTraceStats(Stats::Group *parent);
/** Number of register dependencies recorded during tracing */

12
src/cpu/o3/rename.hh
View File

@@ -295,7 +295,8 @@ class DefaultRename
* the instruction's sequence number, the arch register, the old physical
* register for that arch. register, and the new physical register.
*/
struct RenameHistory {
struct RenameHistory
{
RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
PhysRegIdPtr _newPhysReg,
PhysRegIdPtr _prevPhysReg)
@@ -388,7 +389,8 @@ class DefaultRename
/** Structures whose free entries impact the amount of instructions that
* can be renamed.
*/
struct FreeEntries {
struct FreeEntries
{
unsigned iqEntries;
unsigned robEntries;
unsigned lqEntries;
@@ -407,7 +409,8 @@ class DefaultRename
bool emptyROB[Impl::MaxThreads];
/** Source of possible stalls. */
struct Stalls {
struct Stalls
{
bool iew;
bool commit;
};
@@ -478,7 +481,8 @@ class DefaultRename
*/
inline void incrFullStat(const FullSource &source);
struct RenameStats : public Stats::Group {
struct RenameStats : public Stats::Group
{
RenameStats(Stats::Group *parent);
/** Stat for total number of cycles spent squashing. */

3
src/cpu/o3/rob.hh
View File

@@ -321,7 +321,8 @@ class ROB
ThreadID numThreads;
struct ROBStats : public Stats::Group {
struct ROBStats : public Stats::Group
{
ROBStats(Stats::Group *parent);
// The number of rob_reads

3
src/cpu/o3/store_set.hh
View File

@@ -37,7 +37,8 @@
#include "base/types.hh"
#include "cpu/inst_seq.hh"
struct ltseqnum {
struct ltseqnum
{
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
{
return lhs > rhs;

3
src/cpu/o3/thread_state.hh
View File

@@ -61,7 +61,8 @@ class Process;
* thread's process, such as syscalls and checking valid addresses.
*/
template <class Impl>
struct O3ThreadState : public ThreadState {
struct O3ThreadState : public ThreadState
{
typedef ThreadContext::Status Status;
typedef typename Impl::O3CPU O3CPU;

3
src/cpu/pred/bi_mode.hh
View File

@@ -65,7 +65,8 @@ class BiModeBP : public BPredUnit
private:
void updateGlobalHistReg(ThreadID tid, bool taken);
struct BPHistory {
struct BPHistory
{
unsigned globalHistoryReg;
// was the taken array's prediction used?
// true: takenPred used

6
src/cpu/pred/bpred_unit.hh
View File

@@ -185,7 +185,8 @@ class BPredUnit : public SimObject
void dump();
private:
struct PredictorHistory {
struct PredictorHistory
{
/**
* Makes a predictor history struct that contains any
* information needed to update the predictor, BTB, and RAS.
@@ -277,7 +278,8 @@ class BPredUnit : public SimObject
/** The indirect target predictor. */
IndirectPredictor * iPred;
struct BPredUnitStats : public Stats::Group {
struct BPredUnitStats : public Stats::Group
{
BPredUnitStats(Stats::Group *parent);
/** Stat for number of BP lookups. */

3
src/cpu/pred/loop_predictor.hh
View File

@@ -83,7 +83,8 @@ class LoopPredictor : public SimObject
const unsigned initialLoopAge;
const bool optionalAgeReset;
struct LoopPredictorStats : public Stats::Group {
struct LoopPredictorStats : public Stats::Group
{
LoopPredictorStats(Stats::Group *parent);
Stats::Scalar correct;
Stats::Scalar wrong;

3
src/cpu/pred/multiperspective_perceptron.cc
View File

@@ -249,7 +249,8 @@ MultiperspectivePerceptron::findBest(ThreadID tid,
if (threshold < 0) {
return;
}
struct BestPair {
struct BestPair
{
int index;
int mpreds;
bool operator<(BestPair const &bp) const

9
src/cpu/pred/multiperspective_perceptron.hh
View File

@@ -141,7 +141,8 @@ class MultiperspectivePerceptron : public BPredUnit
/**
* Entry of the branch filter
*/
struct FilterEntry {
struct FilterEntry
{
/** Has this branch been taken at least once? */
bool seenTaken;
/** Has this branch been not taken at least once? */
@@ -215,7 +216,8 @@ class MultiperspectivePerceptron : public BPredUnit
/**
* Base class to implement the predictor tables.
*/
struct HistorySpec {
struct HistorySpec
{
/** First parameter */
const int p1;
/** Second parameter */
@@ -287,7 +289,8 @@ class MultiperspectivePerceptron : public BPredUnit
static int xlat4[];
/** History data is kept for each thread */
struct ThreadData {
struct ThreadData
{
ThreadData(int num_filter, int n_local_histories,
int local_history_length, int assoc,
const std::vector<std::vector<int>> &blurrypath_bits,

6
src/cpu/pred/multiperspective_perceptron_tage.hh
View File

@@ -52,7 +52,8 @@ class MPP_TAGE : public TAGEBase
{
std::vector<unsigned int> tunedHistoryLengths;
public:
struct BranchInfo : public TAGEBase::BranchInfo {
struct BranchInfo : public TAGEBase::BranchInfo
{
BranchInfo(TAGEBase &tage) : TAGEBase::BranchInfo(tage)
{}
virtual ~BranchInfo()
@@ -145,7 +146,8 @@ class MPP_StatisticalCorrector : public StatisticalCorrector
};
public:
struct BranchInfo : public StatisticalCorrector::BranchInfo {
struct BranchInfo : public StatisticalCorrector::BranchInfo
{
virtual ~BranchInfo()
{}
};

3
src/cpu/pred/simple_indirect.hh
View File

@@ -87,7 +87,8 @@ class SimpleIndirectPredictor : public IndirectPredictor
};
struct ThreadInfo {
struct ThreadInfo
{
ThreadInfo() : headHistEntry(0), ghr(0) { }
std::deque<HistoryEntry> pathHist;

6
src/cpu/pred/statistical_corrector.hh
View File

@@ -66,7 +66,8 @@ class StatisticalCorrector : public SimObject
}
}
// histories used for the statistical corrector
struct SCThreadHistory {
struct SCThreadHistory
{
SCThreadHistory() {
bwHist = 0;
numOrdinalHistories = 0;
@@ -182,7 +183,8 @@ class StatisticalCorrector : public SimObject
int8_t firstH;
int8_t secondH;
struct StatisticalCorrectorStats : public Stats::Group {
struct StatisticalCorrectorStats : public Stats::Group
{
StatisticalCorrectorStats(Stats::Group *parent);
Stats::Scalar correct;
Stats::Scalar wrong;

3
src/cpu/pred/tage.hh
View File

@@ -60,7 +60,8 @@ class TAGE: public BPredUnit
protected:
TAGEBase *tage;
struct TageBranchInfo {
struct TageBranchInfo
{
TAGEBase::BranchInfo *tageBranchInfo;
TageBranchInfo(TAGEBase &tage) : tageBranchInfo(tage.makeBranchInfo())

6
src/cpu/pred/tage_base.hh
View File

@@ -431,7 +431,8 @@ class TAGEBase : public SimObject
// Keep per-thread histories to
// support SMT.
struct ThreadHistory {
struct ThreadHistory
{
// Speculative path history
// (LSB of branch address)
int pathHist;
@@ -482,7 +483,8 @@ class TAGEBase : public SimObject
bool initialized;
struct TAGEBaseStats : public Stats::Group {
struct TAGEBaseStats : public Stats::Group
{
TAGEBaseStats(Stats::Group *parent, unsigned nHistoryTables);
// stats
Stats::Scalar longestMatchProviderCorrect;

3
src/cpu/pred/tage_sc_l.hh
View File

@@ -63,7 +63,8 @@ class TAGE_SC_L_TAGE : public TAGEBase
const bool truncatePathHist;
public:
struct BranchInfo : public TAGEBase::BranchInfo {
struct BranchInfo : public TAGEBase::BranchInfo
{
bool lowConf;
bool highConf;
bool altConf;

3
src/cpu/pred/tournament.hh
View File

@@ -151,7 +151,8 @@ class TournamentBP : public BPredUnit
* when the BP can use this information to update/restore its
* state properly.
*/
struct BPHistory {
struct BPHistory
{
#ifdef DEBUG
BPHistory()
{ newCount++; }

3
src/cpu/simple/probes/simpoint.hh
View File

@@ -98,7 +98,8 @@ class SimPoint : public ProbeListenerObject
OutputStream *simpointStream;
/** Basic Block information */
struct BBInfo {
struct BBInfo
{
/** Unique ID */
uint64_t id;
/** Num of static insts in BB */

3
src/cpu/simple/timing.hh
View File

@@ -329,7 +329,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
EventFunctionWrapper fetchEvent;
struct IprEvent : Event {
struct IprEvent : Event
{
Packet *pkt;
TimingSimpleCPU *cpu;
IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);

3
src/cpu/testers/traffic_gen/base.hh
View File

@@ -191,7 +191,8 @@ class BaseTrafficGen : public ClockedObject
/** Reqs waiting for response **/
std::unordered_map<RequestPtr,Tick> waitingResp;
struct StatGroup : public Stats::Group {
struct StatGroup : public Stats::Group
{
StatGroup(Stats::Group *parent);
/** Count the number of dropped requests. */

3
src/cpu/testers/traffic_gen/trace_gen.hh
View File

@@ -63,7 +63,8 @@ class TraceGen : public BaseGen
/**
* This struct stores a line in the trace file.
*/
struct TraceElement {
struct TraceElement
{
/** Specifies if the request is to be a read or a write */
MemCmd cmd;

3
src/cpu/testers/traffic_gen/traffic_gen.hh
View File

@@ -100,7 +100,8 @@ class TrafficGen : public BaseTrafficGen
size_t nextState();
/** Struct to represent a probabilistic transition during parsing. */
struct Transition {
struct Transition
{
uint32_t from;
uint32_t to;
double p;

3
src/cpu/thread_state.hh
View File

@@ -43,7 +43,8 @@ class Checkpoint;
* memory, quiesce events, and certain stats. This can be expanded
* to hold more thread-specific stats within it.
*/
struct ThreadState : public Serializable {
struct ThreadState : public Serializable
{
typedef ThreadContext::Status Status;
ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);

6
src/dev/arm/flash_device.hh
View File

@@ -80,12 +80,14 @@ class FlashDevice : public AbstractNVM
};
/** Every logical address maps to a physical block and a physical page*/
struct PageMapEntry {
struct PageMapEntry
{
uint32_t page;
uint32_t block;
};
struct CallBackEntry {
struct CallBackEntry
{
Tick time;
std::function<void()> function;
};

3
src/dev/arm/fvp_base_pwr_ctrl.hh
View File

@@ -114,7 +114,8 @@ class FVPBasePwrCtrl : public BasicPioDevice
PSYSR = 0x10
};
struct Registers {
struct Registers
{
uint32_t ppoffr;
uint32_t pponr;
uint32_t pcoffr;

3
src/dev/arm/gic_v2.hh
View File

@@ -176,7 +176,8 @@ class GicV2 : public BaseGic, public BaseGicRegisters
uint32_t itLines;
/** Registers "banked for each connected processor" per ARM IHI0048B */
struct BankedRegs : public Serializable {
struct BankedRegs : public Serializable
{
/** GICD_I{S,C}ENABLER0
* interrupt enable bits for first 32 interrupts, 1b per interrupt */
uint32_t intEnabled;

51
src/dev/arm/ufs_device.hh
View File

@@ -185,7 +185,8 @@ class UFSHostDevice : public DmaDevice
* As defined in:
* http://www.jedec.org/standards-documents/results/jesd223
*/
struct HCIMem {
struct HCIMem
{
/**
* Specify the host capabilities
*/
@@ -253,7 +254,8 @@ class UFSHostDevice : public DmaDevice
* dWord1: UPIU header DW-1
* dWord2: UPIU header DW-2
*/
struct UTPUPIUHeader {
struct UTPUPIUHeader
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t dWord2;
@@ -267,7 +269,8 @@ class UFSHostDevice : public DmaDevice
* senseDataLen: Sense data length DW-8 U16
* senseData: Sense data field DW-8 to DW-12
*/
struct UTPUPIURSP {
struct UTPUPIURSP
{
struct UTPUPIUHeader header;
uint32_t residualTransferCount;
uint32_t reserved[4];
@@ -283,7 +286,8 @@ class UFSHostDevice : public DmaDevice
* inputParam3: Input param 3 DW-5
* reserved: Reserver DW-6 to DW-7
*/
struct UTPUPIUTaskReq {
struct UTPUPIUTaskReq
{
struct UTPUPIUHeader header;
uint32_t inputParam1;
uint32_t inputParam2;
@@ -298,7 +302,8 @@ class UFSHostDevice : public DmaDevice
* reserved: Reserved for future use DW-2
* size: size of physical segment DW-3
*/
struct UFSHCDSGEntry {
struct UFSHCDSGEntry
{
uint32_t baseAddr;
uint32_t upperAddr;
uint32_t reserved;
@@ -312,7 +317,8 @@ class UFSHostDevice : public DmaDevice
* PRDTable: Physcial Region Descriptor
* All lengths as defined by JEDEC220
*/
struct UTPTransferCMDDesc {
struct UTPTransferCMDDesc
{
uint8_t commandUPIU[128];
uint8_t responseUPIU[128];
struct UFSHCDSGEntry PRDTable[128];
@@ -321,7 +327,8 @@ class UFSHostDevice : public DmaDevice
/**
* UPIU tranfer message.
*/
struct UPIUMessage {
struct UPIUMessage
{
struct UTPUPIUHeader header;
uint32_t dataOffset;
uint32_t dataCount;
@@ -338,7 +345,8 @@ class UFSHostDevice : public DmaDevice
* PRDTableLength: Physical region descriptor length DW-7
* PRDTableOffset: Physical region descriptor offset DW-7
*/
struct UTPTransferReqDesc {
struct UTPTransferReqDesc
{
/**
* struct RequestDescHeader
@@ -347,7 +355,8 @@ class UFSHostDevice : public DmaDevice
* dword2: Descriptor Header DW2
* dword3: Descriptor Header DW3
*/
struct RequestDescHeader {
struct RequestDescHeader
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t dWord2;
@@ -371,7 +380,8 @@ class UFSHostDevice : public DmaDevice
* SCSI reply structure. In here is all the information that is needed to
* build a SCSI reply.
*/
struct SCSIReply {
struct SCSIReply
{
void reset() {
memset(static_cast<void*>(this), 0, sizeof(*this));
}
@@ -391,7 +401,8 @@ class UFSHostDevice : public DmaDevice
* This structure is defined in the SCSI standard, and can also be found in
* the UFS standard. http://www.jedec.org/standards-documents/results/jesd220
*/
struct LUNInfo {
struct LUNInfo
{
uint32_t dWord0;
uint32_t dWord1;
uint32_t vendor0;
@@ -422,7 +433,8 @@ class UFSHostDevice : public DmaDevice
* @filePointer this does not point to a file, but to a position on the disk
* image (which is from the software systems perspective a position in a file)
*/
struct transferInfo {
struct transferInfo
{
std::vector <uint8_t> buffer;
uint32_t size;
uint64_t offset;
@@ -434,7 +446,8 @@ class UFSHostDevice : public DmaDevice
* transfer completion info.
* This information is needed by transferDone to finish the transfer.
*/
struct transferDoneInfo {
struct transferDoneInfo
{
Addr responseStartAddr;
uint32_t reqPos;
struct UTPUPIURSP requestOut;
@@ -448,7 +461,8 @@ class UFSHostDevice : public DmaDevice
/**
* Transfer start information.
*/
struct transferStart {
struct transferStart
{
struct UTPTransferReqDesc* destination;
uint32_t mask;
Addr address;
@@ -460,7 +474,8 @@ class UFSHostDevice : public DmaDevice
/**
* Task start information. This is for the device, so no lun id needed.
*/
struct taskStart {
struct taskStart
{
struct UTPUPIUTaskReq destination;
uint32_t mask;
Addr address;
@@ -472,7 +487,8 @@ class UFSHostDevice : public DmaDevice
* After a SCSI command has been identified, the SCSI resume function will
* handle it. This information will provide context information.
*/
struct SCSIResumeInfo {
struct SCSIResumeInfo
{
struct UTPTransferReqDesc* RequestIn;
int reqPos;
Addr finalAddress;
@@ -485,7 +501,8 @@ class UFSHostDevice : public DmaDevice
* Disk transfer burst information. Needed to allow communication between the
* disk transactions and dma transactions.
*/
struct writeToDiskBurst {
struct writeToDiskBurst
{
Addr start;
uint64_t SCSIDiskOffset;
uint32_t size;

3
src/dev/arm/vgic.hh
View File

@@ -152,7 +152,8 @@ class VGic : public PioDevice
/* State per CPU. EVERYTHING should be in this struct and simply replicated
* N times.
*/
struct vcpuIntData : public Serializable {
struct vcpuIntData : public Serializable
{
vcpuIntData()
: vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),

3
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -371,7 +371,8 @@ class HSAPacketProcessor: public DmaDevice
/**
* Calls getCurrentEntry once the queueEntry has been dmaRead.
*/
struct dma_series_ctx {
struct dma_series_ctx
{
// deal with the fact dma ops can complete out of issue order
uint32_t pkts_ttl;
uint32_t pkts_2_go;

111
src/dev/hsa/kfd_ioctl.h
View File

@@ -29,7 +29,8 @@
#define KFD_IOCTL_MAJOR_VERSION 1
#define KFD_IOCTL_MINOR_VERSION 2
struct kfd_ioctl_get_version_args {
struct kfd_ioctl_get_version_args
{
uint32_t major_version; /* from KFD */
uint32_t minor_version; /* from KFD */
};
@@ -42,7 +43,8 @@ struct kfd_ioctl_get_version_args {
#define KFD_MAX_QUEUE_PERCENTAGE 100
#define KFD_MAX_QUEUE_PRIORITY 15
struct kfd_ioctl_create_queue_args {
struct kfd_ioctl_create_queue_args
{
uint64_t ring_base_address; /* to KFD */
uint64_t write_pointer_address; /* from KFD */
uint64_t read_pointer_address; /* from KFD */
@@ -62,12 +64,14 @@ struct kfd_ioctl_create_queue_args {
uint32_t ctl_stack_size; /* to KFD */
};
struct kfd_ioctl_destroy_queue_args {
struct kfd_ioctl_destroy_queue_args
{
uint32_t queue_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_update_queue_args {
struct kfd_ioctl_update_queue_args
{
uint64_t ring_base_address; /* to KFD */
uint32_t queue_id; /* to KFD */
@@ -76,7 +80,8 @@ struct kfd_ioctl_update_queue_args {
uint32_t queue_priority; /* to KFD */
};
struct kfd_ioctl_set_cu_mask_args {
struct kfd_ioctl_set_cu_mask_args
{
uint32_t queue_id; /* to KFD */
uint32_t num_cu_mask; /* to KFD */
uint64_t cu_mask_ptr; /* to KFD */
@@ -86,7 +91,8 @@ struct kfd_ioctl_set_cu_mask_args {
#define KFD_IOC_CACHE_POLICY_COHERENT 0
#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
struct kfd_ioctl_set_memory_policy_args {
struct kfd_ioctl_set_memory_policy_args
{
uint64_t alternate_aperture_base; /* to KFD */
uint64_t alternate_aperture_size; /* to KFD */
@@ -96,7 +102,8 @@ struct kfd_ioctl_set_memory_policy_args {
uint32_t pad;
};
struct kfd_ioctl_set_trap_handler_args {
struct kfd_ioctl_set_trap_handler_args
{
uint64_t tba_addr;
uint64_t tma_addr;
uint32_t gpu_id; /* to KFD */
@@ -110,7 +117,8 @@ struct kfd_ioctl_set_trap_handler_args {
* In case of GPU reset, the counter should not be affected.
*/
struct kfd_ioctl_get_clock_counters_args {
struct kfd_ioctl_get_clock_counters_args
{
uint64_t gpu_clock_counter; /* from KFD */
uint64_t cpu_clock_counter; /* from KFD */
uint64_t system_clock_counter; /* from KFD */
@@ -122,7 +130,8 @@ struct kfd_ioctl_get_clock_counters_args {
#define NUM_OF_SUPPORTED_GPUS 7
struct kfd_process_device_apertures {
struct kfd_process_device_apertures
{
uint64_t lds_base; /* from KFD */
uint64_t lds_limit; /* from KFD */
uint64_t scratch_base; /* from KFD */
@@ -137,7 +146,8 @@ struct kfd_process_device_apertures {
* kfd_ioctl_get_process_apertures_new instead, which supports
* arbitrary numbers of GPUs.
*/
struct kfd_ioctl_get_process_apertures_args {
struct kfd_ioctl_get_process_apertures_args
{
struct kfd_process_device_apertures
process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
@@ -146,7 +156,8 @@ struct kfd_ioctl_get_process_apertures_args {
uint32_t pad;
};
struct kfd_ioctl_get_process_apertures_new_args {
struct kfd_ioctl_get_process_apertures_new_args
{
/* User allocated. Pointer to struct kfd_process_device_apertures
* filled in by Kernel
*/
@@ -163,23 +174,27 @@ struct kfd_ioctl_get_process_apertures_new_args {
#define MAX_ALLOWED_AW_BUFF_SIZE 4096
#define MAX_ALLOWED_WAC_BUFF_SIZE 128
struct kfd_ioctl_dbg_register_args {
struct kfd_ioctl_dbg_register_args
{
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_dbg_unregister_args {
struct kfd_ioctl_dbg_unregister_args
{
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_dbg_address_watch_args {
struct kfd_ioctl_dbg_address_watch_args
{
uint64_t content_ptr; /* a pointer to the actual content */
uint32_t gpu_id; /* to KFD */
uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
};
struct kfd_ioctl_dbg_wave_control_args {
struct kfd_ioctl_dbg_wave_control_args
{
uint64_t content_ptr; /* a pointer to the actual content */
uint32_t gpu_id; /* to KFD */
uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
@@ -209,7 +224,8 @@ struct kfd_ioctl_dbg_wave_control_args {
*/
#define KFD_SIGNAL_EVENT_LIMIT (4096 + 512)
struct kfd_ioctl_create_event_args {
struct kfd_ioctl_create_event_args
{
uint64_t event_page_offset; /* from KFD */
uint32_t event_trigger_data; /* from KFD - signal events only */
uint32_t event_type; /* to KFD */
@@ -220,22 +236,26 @@ struct kfd_ioctl_create_event_args {
uint32_t event_slot_index; /* from KFD */
};
struct kfd_ioctl_destroy_event_args {
struct kfd_ioctl_destroy_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_set_event_args {
struct kfd_ioctl_set_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_reset_event_args {
struct kfd_ioctl_reset_event_args
{
uint32_t event_id; /* to KFD */
uint32_t pad;
};
struct kfd_memory_exception_failure {
struct kfd_memory_exception_failure
{
uint32_t NotPresent; /* Page not present or supervisor privilege */
uint32_t ReadOnly; /* Write access to a read-only page */
uint32_t NoExecute; /* Execute access to a page marked NX */
@@ -243,7 +263,8 @@ struct kfd_memory_exception_failure {
};
/* memory exception data */
struct kfd_hsa_memory_exception_data {
struct kfd_hsa_memory_exception_data
{
struct kfd_memory_exception_failure failure;
uint64_t va;
uint32_t gpu_id;
@@ -251,7 +272,8 @@ struct kfd_hsa_memory_exception_data {
};
/* Event data */
struct kfd_event_data {
struct kfd_event_data
{
union {
struct kfd_hsa_memory_exception_data memory_exception_data;
}; /* From KFD */
@@ -261,7 +283,8 @@ struct kfd_event_data {
uint32_t pad;
};
struct kfd_ioctl_wait_events_args {
struct kfd_ioctl_wait_events_args
{
uint64_t events_ptr; /* pointed to struct
kfd_event_data array, to KFD */
uint32_t num_events; /* to KFD */
@@ -270,7 +293,8 @@ struct kfd_ioctl_wait_events_args {
uint32_t wait_result; /* from KFD */
};
struct kfd_ioctl_alloc_memory_of_scratch_args {
struct kfd_ioctl_alloc_memory_of_scratch_args
{
uint64_t va_addr; /* to KFD */
uint64_t size; /* to KFD */
uint32_t gpu_id; /* to KFD */
@@ -291,7 +315,8 @@ struct kfd_ioctl_alloc_memory_of_scratch_args {
#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTE_ACCESS (1 << 26)
#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 25)
struct kfd_ioctl_alloc_memory_of_gpu_args {
struct kfd_ioctl_alloc_memory_of_gpu_args
{
uint64_t va_addr; /* to KFD */
uint64_t size; /* to KFD */
uint64_t handle; /* from KFD */
@@ -300,18 +325,21 @@ struct kfd_ioctl_alloc_memory_of_gpu_args {
uint32_t flags;
};
struct kfd_ioctl_free_memory_of_gpu_args {
struct kfd_ioctl_free_memory_of_gpu_args
{
uint64_t handle; /* to KFD */
};
struct kfd_ioctl_map_memory_to_gpu_args {
struct kfd_ioctl_map_memory_to_gpu_args
{
uint64_t handle; /* to KFD */
uint64_t device_ids_array_ptr; /* to KFD */
uint32_t device_ids_array_size; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_unmap_memory_from_gpu_args {
struct kfd_ioctl_unmap_memory_from_gpu_args
{
uint64_t handle; /* to KFD */
uint64_t device_ids_array_ptr; /* to KFD */
uint32_t device_ids_array_size; /* to KFD */
@@ -323,7 +351,8 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
* has been superseded by the pair of get_dmabuf_info and
* import_dmabuf, which is implemented for all supported GPUs.
*/
struct kfd_ioctl_open_graphic_handle_args {
struct kfd_ioctl_open_graphic_handle_args
{
uint64_t va_addr; /* to KFD */
uint64_t handle; /* from KFD */
uint32_t gpu_id; /* to KFD */
@@ -332,14 +361,16 @@ struct kfd_ioctl_open_graphic_handle_args {
uint32_t pad;
};
struct kfd_ioctl_set_process_dgpu_aperture_args {
struct kfd_ioctl_set_process_dgpu_aperture_args
{
uint64_t dgpu_base;
uint64_t dgpu_limit;
uint32_t gpu_id;
uint32_t pad;
};
struct kfd_ioctl_get_dmabuf_info_args {
struct kfd_ioctl_get_dmabuf_info_args
{
uint64_t size; /* from KFD */
uint64_t metadata_ptr; /* to KFD */
uint32_t metadata_size; /* to KFD (space allocated by user)
@@ -349,21 +380,24 @@ struct kfd_ioctl_get_dmabuf_info_args {
uint32_t dmabuf_fd; /* to KFD */
};
struct kfd_ioctl_import_dmabuf_args {
struct kfd_ioctl_import_dmabuf_args
{
uint64_t va_addr; /* to KFD */
uint64_t handle; /* from KFD */
uint32_t gpu_id; /* to KFD */
uint32_t dmabuf_fd; /* to KFD */
};
struct kfd_ioctl_ipc_export_handle_args {
struct kfd_ioctl_ipc_export_handle_args
{
uint64_t handle; /* to KFD */
uint32_t share_handle[4]; /* from KFD */
uint32_t gpu_id; /* to KFD */
uint32_t pad;
};
struct kfd_ioctl_ipc_import_handle_args {
struct kfd_ioctl_ipc_import_handle_args
{
uint64_t handle; /* from KFD */
uint64_t va_addr; /* to KFD */
uint64_t mmap_offset; /* from KFD */
@@ -372,7 +406,8 @@ struct kfd_ioctl_ipc_import_handle_args {
uint32_t pad;
};
struct kfd_ioctl_get_tile_config_args {
struct kfd_ioctl_get_tile_config_args
{
/* to KFD: pointer to tile array */
uint64_t tile_config_ptr;
/* to KFD: pointer to macro tile array */
@@ -395,7 +430,8 @@ struct kfd_ioctl_get_tile_config_args {
*/
};
struct kfd_memory_range {
struct kfd_memory_range
{
uint64_t va_addr;
uint64_t size;
};
@@ -409,7 +445,8 @@ struct kfd_memory_range {
#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT)
#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT)
struct kfd_ioctl_cross_memory_copy_args {
struct kfd_ioctl_cross_memory_copy_args
{
/* to KFD: Process ID of the remote process */
uint32_t pid;
/* to KFD: See above definition */

6
src/dev/net/etherdump.cc
View File

@@ -53,7 +53,8 @@ EtherDump::EtherDump(const Params &p)
#define PCAP_VERSION_MAJOR 2
#define PCAP_VERSION_MINOR 4
struct pcap_file_header {
struct pcap_file_header
{
uint32_t magic;
uint16_t version_major;
uint16_t version_minor;
@@ -63,7 +64,8 @@ struct pcap_file_header {
uint32_t linktype; // data link type (DLT_*)
};
struct pcap_pkthdr {
struct pcap_pkthdr
{
uint32_t seconds;
uint32_t microseconds;
uint32_t caplen; // length of portion present

6
src/dev/net/etherswitch.hh
View File

@@ -117,7 +117,8 @@ class EtherSwitch : public SimObject
class PortFifo : public Serializable
{
protected:
struct EntryOrder {
struct EntryOrder
{
bool operator() (const PortFifoEntry& lhs,
const PortFifoEntry& rhs) const
{
@@ -171,7 +172,8 @@ class EtherSwitch : public SimObject
EventFunctionWrapper txEvent;
};
struct SwitchTableEntry {
struct SwitchTableEntry
{
Interface *interface;
Tick lastUseTime;
};

12
src/dev/net/i8254xGBe_defs.hh
View File

@@ -186,7 +186,8 @@ enum IntTypes
};
// Receive Descriptor struct
struct RxDesc {
struct RxDesc
{
union {
struct {
Addr buf;
@@ -221,7 +222,8 @@ struct RxDesc {
};
};
struct TxDesc {
struct TxDesc
{
uint64_t d1;
uint64_t d2;
};
@@ -294,9 +296,11 @@ inline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); }
inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
struct Regs : public Serializable {
struct Regs : public Serializable
{
template<class T>
struct Reg {
struct Reg
{
T _data;
T operator()() { return _data; }
const Reg<T> &operator=(T d) { _data = d; return *this;}

6
src/dev/net/ns_gige.hh
View File

@@ -58,7 +58,8 @@ const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
/**
* Ethernet device registers
*/
struct dp_regs {
struct dp_regs
{
uint32_t command;
uint32_t config;
uint32_t mear;
@@ -95,7 +96,8 @@ struct dp_regs {
uint32_t tesr;
};
struct dp_rom {
struct dp_rom
{
/**
* for perfect match memory.
* the linux driver doesn't use any other ROM

6
src/dev/net/ns_gige_reg.h
View File

@@ -351,14 +351,16 @@ enum M5ControlRegister {
M5REG_TX_THREAD = 0x00000001
};
struct ns_desc32 {
struct ns_desc32
{
uint32_t link; /* link field to next descriptor in linked list */
uint32_t bufptr; /* pointer to the first fragment or buffer */
uint32_t cmdsts; /* command/status field */
uint32_t extsts; /* extended status field for VLAN and IP info */
};
struct ns_desc64 {
struct ns_desc64
{
uint64_t link; /* link field to next descriptor in linked list */
uint64_t bufptr; /* pointer to the first fragment or buffer */
uint32_t cmdsts; /* command/status field */

3
src/dev/net/sinic.hh
View File

@@ -129,7 +129,8 @@ class Device : public Base
uint64_t RxStatus; // 0x78
} regs;
struct VirtualReg {
struct VirtualReg
{
uint64_t RxData;
uint64_t RxDone;
uint64_t TxData;

12
src/dev/pci/copy_engine_defs.hh
View File

@@ -62,7 +62,8 @@ const uint32_t DESC_CTRL_CP_STS = 0x00000008;
const uint32_t DESC_CTRL_FRAME = 0x00000010;
const uint32_t DESC_CTRL_NULL = 0x00000020;
struct DmaDesc {
struct DmaDesc
{
uint32_t len;
uint32_t command;
Addr src;
@@ -91,7 +92,8 @@ struct DmaDesc {
inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
template<class T>
struct Reg {
struct Reg
{
T _data;
T operator()() { return _data; }
const Reg<T> &operator=(T d) { _data = d; return *this;}
@@ -109,7 +111,8 @@ struct Reg {
};
struct Regs : public Serializable {
struct Regs : public Serializable
{
uint8_t chanCount;
uint8_t xferCap;
@@ -141,7 +144,8 @@ struct Regs : public Serializable {
};
struct ChanRegs : public Serializable {
struct ChanRegs : public Serializable
{
struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00
using Reg<uint16_t>::operator =;
ADD_FIELD16(interrupt_disable,0,1);

6
src/dev/pci/pcireg.h
View File

@@ -307,7 +307,8 @@ union MSIXTable {
};
#define MSIXVECS_PER_PBA 64
struct MSIXPbaEntry {
struct MSIXPbaEntry
{
uint64_t bits;
};
@@ -315,7 +316,8 @@ struct MSIXPbaEntry {
* Defines the PCI Express capability register and its associated bitfields
* for a PCIe device.
*/
struct PXCAP {
struct PXCAP
{
uint8_t data[48];
struct {
uint16_t pxid; /* 0:7 cid

3
src/dev/riscv/plic.hh
View File

@@ -86,7 +86,8 @@ using namespace RiscvISA;
* writing to M mode registers)
*/
struct PlicOutput {
struct PlicOutput
{
std::vector<uint32_t> maxID;
std::vector<uint32_t> maxPriority;
};

9
src/dev/sparc/iob.hh
View File

@@ -86,17 +86,20 @@ class Iob : public PioDevice
NumDeviceIds
};
struct IntMan {
struct IntMan
{
int cpu;
int vector;
};
struct IntCtl {
struct IntCtl
{
bool mask;
bool pend;
};
struct IntBusy {
struct IntBusy
{
bool busy;
int source;
};

3
src/dev/storage/disk_image.hh
View File

@@ -108,7 +108,8 @@ class CowDiskImage : public DiskImage
static const uint32_t VersionMinor;
protected:
struct Sector {
struct Sector
{
uint8_t data[SectorSize];
};
typedef std::unordered_map<uint64_t, Sector *> SectorTable;

3
src/dev/storage/ide_atareg.h
View File

@@ -64,7 +64,8 @@
* ATA_* : ATA only
* ATAPI_* : ATAPI only.
*/
struct ataparams {
struct ataparams
{
/* drive info */
uint16_t atap_config; /* 0: general configuration */
#define WDC_CFG_ATAPI_MASK 0xc000

3
src/dev/virtio/base.hh
View File

@@ -464,7 +464,8 @@ class VirtQueue : public Serializable
typedef uint16_t Flags;
typedef uint16_t Index;
struct M5_ATTR_PACKED Header {
struct M5_ATTR_PACKED Header
{
Flags flags;
Index index;
};

6
src/dev/virtio/block.hh
View File

@@ -81,7 +81,8 @@ class VirtIOBlock : public VirtIODeviceBase
* @note This needs to be changed if the supported feature set
* changes!
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint64_t capacity;
};
Config config;
@@ -122,7 +123,8 @@ class VirtIOBlock : public VirtIODeviceBase
/** @} */
/** VirtIO block device request as sent by guest */
struct M5_ATTR_PACKED BlkRequest {
struct M5_ATTR_PACKED BlkRequest
{
RequestType type;
uint32_t reserved;
uint64_t sector;

3
src/dev/virtio/console.hh
View File

@@ -77,7 +77,8 @@ class VirtIOConsole : public VirtIODeviceBase
* @note This needs to be changed if the multiport feature is
* announced!
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint16_t cols;
uint16_t rows;
};

3
src/dev/virtio/fs9p.cc
View File

@@ -60,7 +60,8 @@
#include "params/VirtIO9PSocket.hh"
#include "sim/system.hh"
struct P9MsgInfo {
struct P9MsgInfo
{
P9MsgInfo(P9MsgType _type, std::string _name)
: type(_type), name(_name) {}

6
src/dev/virtio/fs9p.hh
View File

@@ -50,7 +50,8 @@ struct VirtIO9PBaseParams;
typedef uint8_t P9MsgType;
typedef uint16_t P9Tag;
struct M5_ATTR_PACKED P9MsgHeader {
struct M5_ATTR_PACKED P9MsgHeader
{
/** Length including header */
uint32_t len;
/** Message type */
@@ -120,7 +121,8 @@ class VirtIO9PBase : public VirtIODeviceBase
* @note The fields in this structure depend on the features
* exposed to the guest.
*/
struct M5_ATTR_PACKED Config {
struct M5_ATTR_PACKED Config
{
uint16_t len;
char tag[];
};

15
src/dev/virtio/virtio_ring.h
View File

@@ -59,7 +59,8 @@
#define VIRTIO_RING_F_EVENT_IDX 29
/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
struct vring_desc {
struct vring_desc
{
/* Address (guest-physical). */
uint64_t addr;
/* Length. */
@@ -70,27 +71,31 @@ struct vring_desc {
uint16_t next;
};
struct vring_avail {
struct vring_avail
{
uint16_t flags;
uint16_t idx;
uint16_t ring[];
};
/* u32 is used here for ids for padding reasons. */
struct vring_used_elem {
struct vring_used_elem
{
/* Index of start of used descriptor chain. */
uint32_t id;
/* Total length of the descriptor chain which was used (written to) */
uint32_t len;
};
struct vring_used {
struct vring_used
{
uint16_t flags;
uint16_t idx;
struct vring_used_elem ring[];
};
struct vring {
struct vring
{
unsigned int num;
struct vring_desc *desc;

3
src/kern/linux/helpers.cc
View File

@@ -43,7 +43,8 @@
#include "sim/byteswap.hh"
#include "sim/system.hh"
struct M5_ATTR_PACKED DmesgEntry {
struct M5_ATTR_PACKED DmesgEntry
{
uint64_t ts_nsec;
uint16_t len;
uint16_t text_len;

21
src/kern/linux/linux.hh
View File

@@ -108,7 +108,8 @@ class Linux : public OperatingSystem
static const int _SYS_NMLN = 65;
/// Interface struct for uname().
struct utsname {
struct utsname
{
char sysname[_SYS_NMLN]; //!< System name.
char nodename[_SYS_NMLN]; //!< Node name.
char release[_SYS_NMLN]; //!< OS release.
@@ -117,19 +118,22 @@ class Linux : public OperatingSystem
};
/// Limit struct for getrlimit/setrlimit.
struct rlimit {
struct rlimit
{
uint64_t rlim_cur; //!< soft limit
uint64_t rlim_max; //!< hard limit
};
/// For gettimeofday().
struct timeval {
struct timeval
{
int64_t tv_sec; //!< seconds
int64_t tv_usec; //!< microseconds
};
/// For clock_gettime().
struct timespec {
struct timespec
{
time_t tv_sec; //!< seconds
int64_t tv_nsec; //!< nanoseconds
};
@@ -138,7 +142,8 @@ class Linux : public OperatingSystem
static const int M5_SC_CLK_TCK = 100;
/// For times().
struct tms {
struct tms
{
int64_t tms_utime; //!< user time
int64_t tms_stime; //!< system time
int64_t tms_cutime; //!< user time of children
@@ -146,7 +151,8 @@ class Linux : public OperatingSystem
};
// For writev/readv
struct tgt_iovec {
struct tgt_iovec
{
uint64_t iov_base; // void *
uint64_t iov_len;
};
@@ -211,7 +217,8 @@ class Linux : public OperatingSystem
static const int TGT_RUSAGE_CHILDREN = -1;
static const int TGT_RUSAGE_BOTH = -2;
struct rusage {
struct rusage
{
struct timeval ru_utime; //!< user time used
struct timeval ru_stime; //!< system time used
int64_t ru_maxrss; //!< max rss

3
src/kern/operatingsystem.hh
View File

@@ -38,7 +38,8 @@ class ThreadContext;
/// This struct is used to build target-OS-dependent tables that
/// map the target's flags to the host's flags.
struct SyscallFlagTransTable {
struct SyscallFlagTransTable
{
int tgtFlag; //!< Target system flag value.
int hostFlag; //!< Corresponding host system flag value.
};

3
src/kern/solaris/solaris.hh
View File

@@ -56,7 +56,8 @@ class Solaris : public OperatingSystem
typedef uint32_t nlink_t;
//@}
struct tgt_timespec {
struct tgt_timespec
{
int64_t tv_sec;
int64_t tv_nsec;
};

3
src/mem/abstract_mem.hh
View File

@@ -165,7 +165,8 @@ class AbstractMemory : public ClockedObject
*/
System *_system;
struct MemStats : public Stats::Group {
struct MemStats : public Stats::Group
{
MemStats(AbstractMemory &mem);
void regStats() override;

6
src/mem/cache/prefetch/irregular_stream_buffer.hh vendored
View File

@@ -60,7 +60,8 @@ class IrregularStreamBuffer : public Queued
* Training Unit Entry datatype, it holds the last accessed address and
* its secure flag
*/
struct TrainingUnitEntry : public TaggedEntry {
struct TrainingUnitEntry : public TaggedEntry
{
Addr lastAddress;
bool lastAddressSecure;
};
@@ -68,7 +69,8 @@ class IrregularStreamBuffer : public Queued
AssociativeSet<TrainingUnitEntry> trainingUnit;
/** Address Mapping entry, holds an address and a confidence counter */
struct AddressMapping {
struct AddressMapping
{
Addr address;
SatCounter8 counter;
AddressMapping(unsigned bits) : address(0), counter(bits)

3
src/mem/cache/prefetch/pif.hh vendored
View File

@@ -71,7 +71,8 @@ class PIF : public Queued
* The temporal compactor tracks a small number of the
* most-recently-observed spatial region records.
*/
struct CompactorEntry {
struct CompactorEntry
{
Addr trigger;
std::vector<bool> prec;
std::vector<bool> succ;

3
src/mem/cache/prefetch/queued.hh vendored
View File

@@ -54,7 +54,8 @@ namespace Prefetcher {
class Queued : public Base
{
protected:
struct DeferredPacket : public BaseTLB::Translation {
struct DeferredPacket : public BaseTLB::Translation
{
/** Owner of the packet */
Queued *owner;
/** Prefetch info corresponding to this packet */

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