arch-arm: Consolidate register related files into a directory.

Create a directory called "regs" which holds files, primarily headers,
related to registers, with the exception of registers.hh. Hopefully
registers.hh will go away in the not too distant future, removing this
exception.

Change-Id: I631423c2b09bbcd14b20001380270718aeca619e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41737
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/SConscript

@@ -81,7 +81,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('freebsd/fs_workload.cc')
     Source('freebsd/se_workload.cc')
     Source('fs_workload.cc')
-    Source('miscregs.cc')
+    Source('regs/misc.cc')
     Source('mmu.cc')
     Source('nativetrace.cc')
     Source('pauth_helpers.cc')

src/arch/arm/aapcs32.hh

@@ -33,7 +33,7 @@
 #include <type_traits>
 #include <utility>
 
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "base/intmath.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/aapcs64.hh

@@ -33,7 +33,7 @@
 #include <type_traits>
 #include <utility>
 
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "base/intmath.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/decoder.hh

@@ -43,7 +43,7 @@
 
 #include <cassert>
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "arch/generic/decode_cache.hh"
 #include "arch/generic/decoder.hh"

src/arch/arm/fastmodel/iris/interrupts.cc

@@ -29,8 +29,8 @@
 
 #include "arch/arm/fastmodel/iris/thread_context.hh"
 #include "arch/arm/interrupts.hh"
-#include "arch/arm/miscregs.hh"
-#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/regs/misc.hh"
+#include "arch/arm/regs/misc_types.hh"
 #include "arch/arm/types.hh"
 #include "params/IrisInterrupts.hh"
 

src/arch/arm/fastmodel/iris/isa.cc

@@ -27,7 +27,7 @@
 
 #include "arch/arm/fastmodel/iris/isa.hh"
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/thread_context.hh"
 #include "params/IrisISA.hh"
 #include "sim/serialize.hh"

src/arch/arm/faults.hh

@@ -42,8 +42,8 @@
 #ifndef __ARM_FAULTS_HH__
 #define __ARM_FAULTS_HH__
 
-#include "arch/arm/miscregs.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "base/logging.hh"
 #include "sim/faults.hh"

src/arch/arm/freebsd/se_workload.hh

@@ -34,8 +34,8 @@
 #ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
 #define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/freebsd/freebsd.hh"
+#include "arch/arm/regs/cc.hh"
 #include "arch/arm/se_workload.hh"
 #include "params/ArmEmuFreebsd.hh"
 #include "sim/syscall_desc.hh"

src/arch/arm/htm.cc

@@ -37,8 +37,8 @@
 
 #include "arch/arm/htm.hh"
 
-#include "arch/arm/intregs.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/thread_context.hh"
 
 void

src/arch/arm/htm.hh

@@ -44,8 +44,8 @@
  * ISA-specific types for hardware transactional memory.
  */
 
-#include "arch/arm/intregs.hh"
 #include "arch/arm/registers.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/generic/htm.hh"
 #include "base/types.hh"
 

src/arch/arm/insts/fplib.hh

@@ -49,7 +49,7 @@
 
 #include <stdint.h>
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 
 namespace ArmISA
 {

src/arch/arm/insts/vfp.hh

@@ -43,7 +43,7 @@
 #include <cmath>
 
 #include "arch/arm/insts/misc.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 
 namespace ArmISA
 {

src/arch/arm/interrupts.hh

@@ -43,8 +43,8 @@
 
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
 #include "arch/arm/registers.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/interrupts.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/isa.hh

@@ -42,8 +42,8 @@
 #define __ARCH_ARM_ISA_HH__
 
 #include "arch/arm/isa_device.hh"
-#include "arch/arm/miscregs.hh"
 #include "arch/arm/registers.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"

src/arch/arm/isa/includes.isa

@@ -86,8 +86,8 @@ output decoder {{
 #include "arch/arm/decoder.hh"
 #include "arch/arm/faults.hh"
 #include "arch/arm/insts/sve_macromem.hh"
-#include "arch/arm/intregs.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"

src/arch/arm/isa_device.cc

@@ -37,7 +37,7 @@
 
 #include "arch/arm/isa_device.hh"
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "base/logging.hh"
 
 namespace ArmISA

src/arch/arm/isa_device.hh

@@ -67,7 +67,7 @@ class BaseISADevice
     /**
      * Write to a system register belonging to this device.
      *
-     * @param misc_reg Register number (see miscregs.hh)
+     * @param misc_reg Register number (see regs/misc.hh)
      * @param val Value to store
      */
     virtual void setMiscReg(int misc_reg, RegVal val) = 0;
@@ -75,7 +75,7 @@ class BaseISADevice
     /**
      * Read a system register belonging to this device.
      *
-     * @param misc_reg Register number (see miscregs.hh)
+     * @param misc_reg Register number (see regs/misc.hh)
      * @return Register value.
      */
     virtual RegVal readMiscReg(int misc_reg) = 0;

src/arch/arm/kvm/armv8_cpu.hh

@@ -41,9 +41,9 @@
 #include <set>
 #include <vector>
 
-#include "arch/arm/intregs.hh"
 #include "arch/arm/kvm/base_cpu.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/misc.hh"
 
 struct ArmV8KvmCPUParams;
 

src/arch/arm/locked_mem.hh

@@ -48,8 +48,8 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "arch/arm/miscregs.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/utility.hh"
 #include "debug/LLSC.hh"
 #include "mem/packet.hh"

src/arch/arm/nativetrace.cc

@@ -40,9 +40,9 @@
 
 #include "arch/arm/nativetrace.hh"
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/thread_context.hh"
 #include "debug/ExecRegDelta.hh"
 #include "params/ArmNativeTrace.hh"

src/arch/arm/pmu.hh

@@ -116,14 +116,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice
     /**
      * Set a register within the PMU.
      *
-     * @param misc_reg Register number (see miscregs.hh)
+     * @param misc_reg Register number (see regs/misc.hh)
      * @param val Value to store
      */
     void setMiscReg(int misc_reg, RegVal val) override;
     /**
      * Read a register within the PMU.
      *
-     * @param misc_reg Register number (see miscregs.hh)
+     * @param misc_reg Register number (see regs/misc.hh)
      * @return Register value.
      */
     RegVal readMiscReg(int misc_reg) override;

src/arch/arm/process.cc

@@ -40,9 +40,9 @@
 
 #include "arch/arm/process.hh"
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "base/loader/elf_object.hh"
 #include "base/loader/object_file.hh"

src/arch/arm/process.hh

@@ -44,7 +44,7 @@
 #include <string>
 #include <vector>
 
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "base/loader/object_file.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"

src/arch/arm/registers.hh

@@ -41,7 +41,7 @@
 #ifndef __ARCH_ARM_REGISTERS_HH__
 #define __ARCH_ARM_REGISTERS_HH__
 
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 

src/arch/arm/regs/cc.hh

@@ -35,8 +35,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_CCREGS_HH__
-#define __ARCH_ARM_CCREGS_HH__
+#ifndef __ARCH_ARM_REGS_CC_HH__
+#define __ARCH_ARM_REGS_CC_HH__
 
 namespace ArmISA
 {
@@ -83,4 +83,4 @@ enum ConditionCode
 
 }
 
-#endif // __ARCH_ARM_CCREGS_HH__
+#endif // __ARCH_ARM_REGS_CC_HH__

src/arch/arm/regs/int.hh

@@ -40,8 +40,8 @@
 
 #include <cassert>
 
-#ifndef __ARCH_ARM_INTREGS_HH__
-#define __ARCH_ARM_INTREGS_HH__
+#ifndef __ARCH_ARM_REGS_INT_HH__
+#define __ARCH_ARM_REGS_INT_HH__
 
 #include "arch/arm/types.hh"
 

src/arch/arm/regs/misc.cc

@@ -35,7 +35,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 
 #include <tuple>
 

src/arch/arm/regs/misc.hh

@@ -38,13 +38,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_MISCREGS_HH__
-#define __ARCH_ARM_MISCREGS_HH__
+#ifndef __ARCH_ARM_REGS_MISC_HH__
+#define __ARCH_ARM_REGS_MISC_HH__
 
 #include <bitset>
 #include <tuple>
 
-#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/regs/misc_types.hh"
 #include "base/compiler.hh"
 #include "dev/arm/generic_timer_miscregs_types.hh"
 
@@ -2280,4 +2280,4 @@ namespace ArmISA
 
 }
 
-#endif // __ARCH_ARM_MISCREGS_HH__
+#endif // __ARCH_ARM_REGS_MISC_HH__

src/arch/arm/regs/misc_types.hh

@@ -38,8 +38,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
-#define __ARCH_ARM_MISCREGS_TYPES_HH__
+#ifndef __ARCH_ARM_REGS_MISC_TYPES_HH__
+#define __ARCH_ARM_REGS_MISC_TYPES_HH__
 
 #include "base/bitunion.hh"
 
@@ -344,7 +344,8 @@ namespace ArmISA
                                 // (AArch64 SCTLR_EL1 only)
         Bitfield<23>   span;    // Set Priviledge Access Never on taking
                                 // an exception
-        Bitfield<23>   xp;      // Extended page table enable (dropped in ARMv7)
+        Bitfield<23>   xp;      // Extended page table enable
+                                // (dropped in ARMv7)
         Bitfield<22>   u;       // Alignment (dropped in ARMv7)
         Bitfield<21>   fi;      // Fast interrupts configuration enable
                                 // (ARMv7 only)
@@ -369,7 +370,8 @@ namespace ArmISA
         Bitfield<12>   i;       // Instruction cache enable
         Bitfield<11>   z;       // Branch prediction enable (ARMv7 only)
         Bitfield<10>   sw;      // SWP/SWPB enable (ARMv7 only)
-        Bitfield<9, 8> rs;      // Deprecated protection bits (dropped in ARMv7)
+        Bitfield<9, 8> rs;      // Deprecated protection bits
+                                // (dropped in ARMv7)
         Bitfield<9>    uma;     // User mask access (AArch64 SCTLR_EL1 only)
         Bitfield<8>    sed;     // SETEND disable
                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
@@ -785,4 +787,4 @@ namespace ArmISA
 
 }
 
-#endif // __ARCH_ARM_MISCREGS_TYPES_HH__
+#endif // __ARCH_ARM_REGS_MISC_TYPES_HH__

src/arch/arm/self_debug.cc

@@ -38,7 +38,7 @@
 #include "arch/arm/self_debug.hh"
 
 #include "arch/arm/faults.hh"
-#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/regs/misc_types.hh"
 #include "base/bitfield.hh"
 
 using namespace ArmISA;

src/arch/arm/self_debug.hh

@@ -40,7 +40,7 @@
 
 
 #include "arch/arm/faults.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/types.hh"
 #include "arch/arm/utility.hh"

src/arch/arm/semihosting.hh

@@ -45,7 +45,7 @@
 #include <utility>
 #include <vector>
 
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/utility.hh"
 #include "cpu/thread_context.hh"
 #include "mem/port_proxy.hh"

src/arch/arm/table_walker.hh

@@ -41,7 +41,7 @@
 #include <list>
 
 #include "arch/arm/faults.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
 #include "mem/request.hh"

src/arch/arm/tracers/tarmac_base.cc

@@ -40,7 +40,7 @@
 #include <algorithm>
 #include <string>
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "cpu/reg_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/tracers/tarmac_record.hh

@@ -45,7 +45,7 @@
 
 #include <memory>
 
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/tracers/tarmac_base.hh"
 #include "base/printable.hh"
 #include "config/the_isa.hh"

src/arch/arm/utility.cc

@@ -39,12 +39,12 @@
 
 #include <memory>
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/faults.hh"
 #include "arch/arm/interrupts.hh"
-#include "arch/arm/intregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/mmu.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/int.hh"
 #include "arch/arm/system.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"

src/arch/arm/utility.hh

@@ -42,9 +42,9 @@
 #ifndef __ARCH_ARM_UTILITY_HH__
 #define __ARCH_ARM_UTILITY_HH__
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/misc.hh"
 #include "arch/arm/types.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"