derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch: Eliminate the GuestByteOrder constant.

Browse Source 
Most ISAs used that constant exactly once, when setting up a Process.
This change just propogates the constant to the one place it's used. In
MIPS, the endianness is hard coded as little. There were some checks
which would change the behavior if the endianness was big. This change
removes that dead code. If someone wants to add support for big endian
MIPS, they can go back and add in the small bits of code that would be
required. It's likely the existing big endian support was incomplete and
not tested, so it's probably best for someone interested in it to start
fresh anyway.

Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40178
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-01-29 23:32:26 -08:00
parent 773368d68d
commit e0039d1eab
14 changed files with 11 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/isa_traits.hh
View File

@@ -43,12 +43,9 @@
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace ArmISA
{
const ByteOrder GuestByteOrder = ByteOrder::little;
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
} // namespace ArmISA

2
src/arch/arm/process.cc
View File

@@ -429,7 +429,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxillary vector

5
src/arch/mips/isa/decoder.isa
View File

@@ -1532,10 +1532,7 @@ decode OPCODE_HI default Unknown::unknown() {
if (Rs<2:0> == 0) {
Fd_ud = Fs_ud;
} else if (Rs<2:0> == 4) {
if (GuestByteOrder == ByteOrder::big)
Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
else
Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
} else {
Fd_ud = Fd_ud;
}

4
src/arch/mips/isa/formats/mem.isa
View File

@@ -498,8 +498,6 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
uint32_t mem_word = Mem_uw;
uint32_t unalign_addr = Rs + disp;
uint32_t byte_offset = unalign_addr & 3;
if (GuestByteOrder == ByteOrder::big)
byte_offset ^= 3;
'''
memacc_code = decl_code + memacc_code
@@ -516,8 +514,6 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
uint32_t mem_word = 0;
uint32_t unaligned_addr = Rs + disp;
uint32_t byte_offset = unaligned_addr & 3;
if (GuestByteOrder == ByteOrder::big)
byte_offset ^= 3;
fault = readMemAtomicLE(xc, traceData, EA, mem_word, memAccessFlags);
'''
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'

3
src/arch/mips/isa_traits.hh
View File

@@ -31,13 +31,10 @@
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace MipsISA
{
const ByteOrder GuestByteOrder = ByteOrder::little;
const Addr PageShift = 13;
const Addr PageBytes = 1ULL << PageShift;

3
src/arch/mips/process.cc
View File

@@ -37,6 +37,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
@@ -184,7 +185,7 @@ MipsProcess::argsInit(int pageSize)
// Copy the aux vector
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}

3
src/arch/power/isa_traits.hh
View File

@@ -32,13 +32,10 @@
#define __ARCH_POWER_ISA_TRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace PowerISA
{
const ByteOrder GuestByteOrder = ByteOrder::big;
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;

3
src/arch/power/process.cc
View File

@@ -39,6 +39,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -251,7 +252,7 @@ PowerProcess::argsInit(int intSize, int pageSize)
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector

3
src/arch/riscv/isa_traits.hh
View File

@@ -43,13 +43,10 @@
#define __ARCH_RISCV_ISA_TRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace RiscvISA
{
const ByteOrder GuestByteOrder = ByteOrder::little;
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;

2
src/arch/riscv/process.cc
View File

@@ -198,7 +198,7 @@ RiscvProcess::argsInit(int pageSize)
Addr sp = memState->getStackMin();
const auto pushOntoStack =
[this, &sp](IntType data) {
initVirtMem->write(sp, data, GuestByteOrder);
initVirtMem->write(sp, data, ByteOrder::little);
sp += sizeof(data);
};

3
src/arch/sparc/isa_traits.hh
View File

@@ -30,13 +30,10 @@
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace SparcISA
{
const ByteOrder GuestByteOrder = ByteOrder::big;
const Addr PageShift = 13;
const Addr PageBytes = 1ULL << PageShift;

3
src/arch/sparc/process.cc
View File

@@ -42,6 +42,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -326,7 +327,7 @@ SparcProcess::argsInit(int pageSize)
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}

3
src/arch/x86/isa_traits.hh
View File

@@ -39,12 +39,9 @@
#define __ARCH_X86_ISATRAITS_HH__
#include "base/types.hh"
#include "sim/byteswap.hh"
namespace X86ISA
{
const ByteOrder GuestByteOrder = ByteOrder::little;
const Addr PageShift = 12;
const Addr PageBytes = 1ULL << PageShift;
}

3
src/arch/x86/process.cc
View File

@@ -60,6 +60,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
@@ -961,7 +962,7 @@ X86Process::argsInit(int pageSize,
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
// Write out the terminating zeroed auxiliary vector