diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 83d35aaf19..6c858ccd45 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -43,12 +43,9 @@ #define __ARCH_ARM_ISA_TRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace ArmISA { - const ByteOrder GuestByteOrder = ByteOrder::little; - const Addr PageShift = 12; const Addr PageBytes = 1ULL << PageShift; } // namespace ArmISA diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 91df4c939d..0bfbda105d 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -429,7 +429,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) //Copy the aux stuff Addr auxv_array_end = auxv_array_base; for (const auto &aux: auxv) { - initVirtMem->write(auxv_array_end, aux, GuestByteOrder); + initVirtMem->write(auxv_array_end, aux, ByteOrder::little); auxv_array_end += sizeof(aux); } //Write out the terminating zeroed auxillary vector diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index e5613f52b2..ea2b43a839 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -1532,10 +1532,7 @@ decode OPCODE_HI default Unknown::unknown() { if (Rs<2:0> == 0) { Fd_ud = Fs_ud; } else if (Rs<2:0> == 4) { - if (GuestByteOrder == ByteOrder::big) - Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; - else - Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; + Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; } else { Fd_ud = Fd_ud; } diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index ac56803c06..267d5e838f 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -498,8 +498,6 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; uint32_t mem_word = Mem_uw; uint32_t unalign_addr = Rs + disp; uint32_t byte_offset = unalign_addr & 3; - if (GuestByteOrder == ByteOrder::big) - byte_offset ^= 3; ''' memacc_code = decl_code + memacc_code @@ -516,8 +514,6 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; uint32_t mem_word = 0; uint32_t unaligned_addr = Rs + disp; uint32_t byte_offset = unaligned_addr & 3; - if (GuestByteOrder == ByteOrder::big) - byte_offset ^= 3; fault = readMemAtomicLE(xc, traceData, EA, mem_word, memAccessFlags); ''' memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index fc87530564..541ed6371b 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -31,13 +31,10 @@ #define __ARCH_MIPS_ISA_TRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace MipsISA { -const ByteOrder GuestByteOrder = ByteOrder::little; - const Addr PageShift = 13; const Addr PageBytes = 1ULL << PageShift; diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index e2f2bb9630..0439d0971b 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -37,6 +37,7 @@ #include "mem/page_table.hh" #include "params/Process.hh" #include "sim/aux_vector.hh" +#include "sim/byteswap.hh" #include "sim/process.hh" #include "sim/process_impl.hh" #include "sim/syscall_return.hh" @@ -184,7 +185,7 @@ MipsProcess::argsInit(int pageSize) // Copy the aux vector Addr auxv_array_end = auxv_array_base; for (const auto &aux: auxv) { - initVirtMem->write(auxv_array_end, aux, GuestByteOrder); + initVirtMem->write(auxv_array_end, aux, ByteOrder::little); auxv_array_end += sizeof(aux); } diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh index 24660910f0..e6e7a67fa2 100644 --- a/src/arch/power/isa_traits.hh +++ b/src/arch/power/isa_traits.hh @@ -32,13 +32,10 @@ #define __ARCH_POWER_ISA_TRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace PowerISA { -const ByteOrder GuestByteOrder = ByteOrder::big; - const Addr PageShift = 12; const Addr PageBytes = 1ULL << PageShift; diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index 26d28a8429..5cdd299886 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -39,6 +39,7 @@ #include "mem/page_table.hh" #include "params/Process.hh" #include "sim/aux_vector.hh" +#include "sim/byteswap.hh" #include "sim/process_impl.hh" #include "sim/syscall_return.hh" #include "sim/system.hh" @@ -251,7 +252,7 @@ PowerProcess::argsInit(int intSize, int pageSize) //Copy the aux stuff Addr auxv_array_end = auxv_array_base; for (const auto &aux: auxv) { - initVirtMem->write(auxv_array_end, aux, GuestByteOrder); + initVirtMem->write(auxv_array_end, aux, ByteOrder::big); auxv_array_end += sizeof(aux); } //Write out the terminating zeroed auxilliary vector diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh index 58fdbe9d52..d07ffa205b 100644 --- a/src/arch/riscv/isa_traits.hh +++ b/src/arch/riscv/isa_traits.hh @@ -43,13 +43,10 @@ #define __ARCH_RISCV_ISA_TRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace RiscvISA { -const ByteOrder GuestByteOrder = ByteOrder::little; - const Addr PageShift = 12; const Addr PageBytes = 1ULL << PageShift; diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index 6718b059a1..edfbf4bfee 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -198,7 +198,7 @@ RiscvProcess::argsInit(int pageSize) Addr sp = memState->getStackMin(); const auto pushOntoStack = [this, &sp](IntType data) { - initVirtMem->write(sp, data, GuestByteOrder); + initVirtMem->write(sp, data, ByteOrder::little); sp += sizeof(data); }; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index ca96b3b1cc..895b7d5ac6 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -30,13 +30,10 @@ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace SparcISA { -const ByteOrder GuestByteOrder = ByteOrder::big; - const Addr PageShift = 13; const Addr PageBytes = 1ULL << PageShift; diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 191cbf2e64..e40cb0640e 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -42,6 +42,7 @@ #include "mem/page_table.hh" #include "params/Process.hh" #include "sim/aux_vector.hh" +#include "sim/byteswap.hh" #include "sim/process_impl.hh" #include "sim/syscall_return.hh" #include "sim/system.hh" @@ -326,7 +327,7 @@ SparcProcess::argsInit(int pageSize) // Copy the aux stuff Addr auxv_array_end = auxv_array_base; for (const auto &aux: auxv) { - initVirtMem->write(auxv_array_end, aux, GuestByteOrder); + initVirtMem->write(auxv_array_end, aux, ByteOrder::big); auxv_array_end += sizeof(aux); } diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index b959ef319f..d1dd3922ae 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -39,12 +39,9 @@ #define __ARCH_X86_ISATRAITS_HH__ #include "base/types.hh" -#include "sim/byteswap.hh" namespace X86ISA { - const ByteOrder GuestByteOrder = ByteOrder::little; - const Addr PageShift = 12; const Addr PageBytes = 1ULL << PageShift; } diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 20c78bad47..2b25fb2378 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -60,6 +60,7 @@ #include "mem/page_table.hh" #include "params/Process.hh" #include "sim/aux_vector.hh" +#include "sim/byteswap.hh" #include "sim/process_impl.hh" #include "sim/syscall_desc.hh" #include "sim/syscall_return.hh" @@ -961,7 +962,7 @@ X86Process::argsInit(int pageSize, // Copy the aux stuff Addr auxv_array_end = auxv_array_base; for (const auto &aux: auxv) { - initVirtMem->write(auxv_array_end, aux, GuestByteOrder); + initVirtMem->write(auxv_array_end, aux, ByteOrder::little); auxv_array_end += sizeof(aux); } // Write out the terminating zeroed auxiliary vector