derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
20,464 Commits 2 Branches 0 Tags
29fa894e19b3a00b980ea70b379be5763620a1fc
Commit Graph

597 Commits

Author SHA1 Message Date
Giacomo Travaglini
b355baac93 dev-arm: Treat GICv3 reserved addresses as RES0 
According to the GIC specification (IHI0069) reserved addresses in the
GIC memory map are treated as RES0.  We allow to disable this behaviour
and panic instead (reserved_res0 = False, which is what we have been
doing so far) to catch development bugs (in gem5 and in the guest SW)

Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71138
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-06-05 15:01:59 +00:00
Richard Cooper
ed9effca73 dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn 
Writes to the GICD_IGROUPRn registers are currently applied using the
`|=` operator, allowing bits to be set but not cleared. According to
the specification [1] this register should allow direct writes.

This patch changes the logic to write the new value directly to the
register.

[1] https://developer.arm.com/documentation/ihi0048/latest/

Change-Id: Ia5f17d05530263d7e918ff33576daaf8165c25c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69682
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-04-13 21:09:36 +00:00
Richard Cooper
06637a29e5 arch-arm: Add more detailed debug messages to GICv2. 
Converted the generic DPRINTF messages for the GICv2 register reads
and writes (showing only the memory mapped address) to finer grained
DPRINTF messages showing the names of the mapped registers being
accessed.

This change is intended to make it easier to debug the GIC setup from
the gem5 debug trace.

Change-Id: Ic418b2ea8438fed6a5a810ebc0b686cd4c891cb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69681
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2023-04-13 21:09:36 +00:00
Giacomo Travaglini
e73655d038 misc: Use python f-strings for string formatting 
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
 2023-03-16 09:05:29 +00:00
Gabriel Busnot
ba19f967d7 sim: Use ref constructor of MemberEventWrapper everywhere 
Change-Id: I77989aa7318142634c771c558293138e7b1e8e51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67657
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2023-03-13 06:47:09 +00:00
Gabriel Busnot
1bb8cd3d44 sim: Switch from EventWrapper to MemberEventWrapper before deprec 
Change-Id: I25c81787d522a0dd063112b6727669da46e0f0e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67655
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-03-13 06:47:09 +00:00
Gabriel Busnot
7f4c92c910 mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner 
Change-Id: I29214278c3dd4829c89a6f7c93214b8123912e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67452
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2023-02-03 06:11:45 +00:00
Daniel R. Carvalho
5f5aae8940 dev: Remove a couple of deprecated namespaces 
These namespaces have gone through the deprecation period
and can now be removed: Sinic, SCMI, Ps2, Regs, Keyboard,
Mouse, TxdOp, iGbReg, CopyEngineReg.

Change-Id: Icfaf458bffca2658650318508c0bb376719cf911
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67370
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-01-17 09:16:20 +00:00
Giacomo Travaglini
ed6cf2eced dev-arm: Allow GICv3 to be externally(publicly) updated 
Change-Id: Ifa7b745ea11e74c17024c22ae993b6103eecb744
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66271
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-12-05 10:50:42 +00:00
Giacomo Travaglini
0df37a33f6 arch-arm: Setup TC/ISA at construction time 2nd attempt 
This partly reverts commit ec75787aef
by fixing the original problem noted by Bobby (long regressions):

setupThreadContext has to be implemented otherswise the GICv3 cpu interface
will end up holding old references when switching TC/ISAs.

This new implementation is still setting up the cpu interface reference
in the ISA only when it is required, but it is storing the
TC/ISA reference within the interface every time the ISA::setupThreadContext
gets called.

Change-Id: I2f54f95761d63655162c253e887b872f3718c764
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65931
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-12-04 20:02:10 +00:00
Hoa Nguyen
eac06ad681 python: Fix multiline quotes in a single line 
An example case,
```python
mem_side_port = RequestPort(
    "This port sends requests and " "receives responses"
)
```

This is the residue of running the python formatter.
This is done by finding all tokens matching the regex `"\s"(?![.;"])`
and manually replacing them by empty strings.

Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-11-29 23:44:38 +00:00
Bobby R. Bruce
ec75787aef arch-arm: Revert 'Setup TC/ISA at construction time..' 
Reverts:

dd2f1fb2f8
https://gem5-review.googlesource.com/c/public/gem5/+/65174

and

47bd56ee71
https://gem5-review.googlesource.com/c/public/gem5/+/65291

The 47bd56ee change resulted in the
`SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt`
nightly test stalling. This behavior can be reproduced with:

```
./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py tests/gem5/configs/realview-switcheroo-noncaching-timing.py tests/gem5/resources/arm “$(pwd)”
```

The subsequent change, dd2f1fb2, must be reverted for this change to be
reverted.

Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-11-18 17:46:09 +00:00
Giacomo Travaglini
47bd56ee71 dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface 
We should initialize them as soon as possible to make sure
any Gicv3CPUInterface method uses a valid reference

Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65291
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-11-04 21:25:37 +00:00
Giacomo Travaglini
506bd9d9e7 dev-arm: Use ThreadContext instead if ISA in GICV3 cpu interface 
Some CPU wrappers like the Fastmodel one do extend the
ThreadContext interface in order to retrieve system register
state... By bypassing the TC interface and by using the ISA
instead, we are basically forcing users to extend the ISA
as well to intercept these calls.

So with this patch we are making sure every system register is accessed
(like HCR_EL2 or SCR_EL3) through the thread context. This of course
does not apply to the CPU interface registers as we still use the ISA
storage for them.  In the future we should probably move that storage
from the ISA class to the Gicv3CPUInterface class itself

This is also simplifying Gicv3CPUInterface::isEL3OrMon:
currEL already covers the AArch32 case so no need to
differentiate between AArch32 and AArch64

Change-Id: I446a14a6e12b77e1a62040b3422f79ae52cc9eec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64913
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-10-27 15:33:18 +00:00
Giacomo Travaglini
9a9de78811 dev-arm: Implement System Security Control registers 
This block of system registers is part of the N1 SDP [1]

[1]: https://developer.arm.com/documentation/101489/0000/\
    Programmers-model/System-Security-Control-registers

Change-Id: I2ecf5cd247bd68eddcd359e91f3954070dbffaa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64951
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-10-27 10:33:38 +00:00
Giacomo Travaglini
4db981576e arch-arm: Setup ThreadContext in GICv3 cpu interface 
Change-Id: If019b4b114031f880dff43e05658a162c201ea6a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64912
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-10-27 10:31:10 +00:00
Giacomo Travaglini
7c0ab07ee2 dev-arm: Fix GICv3 GICD_ITARGETSR address range 
According to the GICv3 manual, GICD_ITARGETSR address range goes from
0x0800 to 0x0c00 (as already implemented in the GICv2 model [1])

[1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\
    src/dev/arm/gic_v2.cc#L64

Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64074
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-10-03 17:45:10 +00:00
Giacomo Travaglini
0dc2a87666 dev-arm: Fix PCI range in VExpress_GEM5_Foundation 
When we added the PCI mem range in the VExpress_GEM5_Foundation [1], we
meant to add a 256GiB region starting at 0x40 0000 0000.

By mistake the end address was set to 0x8 0000 0000 rather than
0x80 0000 0000

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/44165

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I848b8fee11fb742939c9343aae4ee5205aa836e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62511
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-09-01 08:07:02 +00:00
Bobby R. Bruce
2bc5a8b71a misc: Run pre-commit run on all files in repo 
The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-08-24 21:47:07 +00:00
Wei-Han Chen
b3781ce93d configs: Add ITS in fastmodel cluster 
There's a gic-its domain in gem5_vexpress_v2 device tree, thus adding ITS
domain in fastmodel cluster config.

Change-Id: Ieb0221fec2e85710531cef1723c492a07f47290a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62212
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-08-10 06:40:35 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files 
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-08-03 09:10:41 +00:00
Giacomo Travaglini
ef2573bc95 arch-arm: Convert to the new faulting logic 
This patch is moving trapping behaviour modelled in
MiscRegOp64::trap to the MiscRegLUTEntry fault callbacks.

Change-Id: Idfca428e9e6669b747de0255888fc8a85a1f5d07
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61683
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-07-29 06:51:11 +00:00
Giacomo Travaglini
5d45c50b48 misc: Add VExpress_GEM5_Foundation bootloader 
The VExpress_GEM5_Foundation platform cannot use the VExpress_GEM5_V2
bootloader as the GIC has a different memory map

A new tarball has been uploaded to dist.gem5.org with the new bootloader

Change-Id: Ie0c16e623c3323b7be2a333cd6b0ffcf891b7b9b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59392
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-07 22:40:47 +00:00
Giacomo Travaglini
776321d2c2 dev-arm: GICD_PIDR2.ArchRev value depends on GIC version 
The GIC architecture specification states the GICD_PIDR2.ArchRev
field is set to 3 for GICv3 and to 4 for GICv4. We bind this
value to the gicv4 parameter

Change-Id: I3ba34bc0b4538b4d5170915a4ee042e534f2590f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59391
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-05-07 22:40:25 +00:00
Giacomo Travaglini
7a9e99400f dev-arm: Gicv3.gicv4 parameter set to False by default 
GICv4 features are not currently implemented so it is more natural
to set it to false by default

VExpress_GEM5_V2 platform assumes a GICv4 memory map therefore
sets it to True

Change-Id: Ib4bd17acd56cd029aacf5578ab0259a6ea1bb30c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59390
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-05-06 16:29:22 +00:00
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict. 
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-28 20:31:21 +00:00
Giacomo Travaglini
4bbcd98598 dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1 
The redirection to CNTHCTL_EL2 is already handled in
ISA::redirectRegVHE

Change-Id: Ia3290c5bdb75c6e45f08a47c1b75881bc52add5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58115
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-25 09:51:56 +00:00
Giacomo Travaglini
9e65dcaeec arch-arm, dev-arm: Implement EL2 Secure Virtual Timer 
Change-Id: Ie4d4ff27b6375593ca4a6f6ae2a5e428ada943be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58112
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-25 09:51:37 +00:00
Giacomo Travaglini
e6797303c4 arch-arm, dev-arm: Implement EL2 Secure Physical Timer 
Change-Id: I052f72695e670fad492079ab912268d05c797100
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58111
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-25 09:50:15 +00:00
Giacomo Travaglini
f1dce36f97 arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer 
Change-Id: I0cc499e1309c35d946c5b9231846263f97bfa2b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-24 16:04:58 +00:00
Giacomo Travaglini
cfc570dd1c dev-arm: Rename GenericTimer interrupts 
The Arm Architecture Reference Manual has moved from
"Armv7-oriented" names for generic timer interrupts to
names more consistent with Armv8 (Exception Levels based).

We are therefore renaming those interrupts as follows:

int_phys_s -> int_el3_phys
int_phys_ns -> int_el1_phys
int_virt -> int_el1_virt
int_hyp -> int_el2_ns_phys

Change-Id: Id6e34a0e4311953938b25bca168a34357e3c8643
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58109
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-24 16:04:58 +00:00
Giacomo Travaglini
9e62fcf2bd dev-arm: Add a KVM Gicv3 model to VExpress_GEM5_Foundation 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ic5cfeeec59630253acb3ccc451553eb4eb7907e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-10 08:59:25 +00:00
Giacomo Travaglini
45a07f1eeb dev-arm: Gicv3 implementation of the Gicv3Registers interface 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iba23604cc6f7d5a1de91c287b4546154fcb20535
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55612
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-03 16:36:29 +00:00
Giacomo Travaglini
342ad01168 dev-arm: Use ArmISA::getAffinity in GICv3 redistributor 
The GICv3 redistributor was reading the MPIDR value and manually
extracting the affinity numbers from it. This is not necessary as there
is already a getAffinity helper function

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6ef150937b51bb065575ed2f432f4f5f0bc38b07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55704
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-03 16:36:11 +00:00
Giacomo Travaglini
c28feb20f2 arch-arm: Templatize MuxingKvmGic to support flexible hierarchy 
By templatizing the MuxingKvmGic we decouple it from the GicV2
class, unlocking non GICv2 (e.g. GICv3) KVM and guest implementations

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I26838903fa7c9f8b9de40678021329cb3390cc74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55611
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-03 16:36:11 +00:00
Giacomo Travaglini
0865772b28 arch-arm, dev-arm: Remove generic BaseGicRegisters interface 
The GICv3 register interface is different from the GICv2 one: from
the presence of redistributor registers up to the system register
implementation of the cpu-interface

We therefore make the current BaseGicRegisters interface GICv2 specific.
We will define a different Gic3Registers interface for GICv3 state
transfer

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I42f15f48cab6e26aaf519e13c2ce70f661801117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55703
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-03 16:36:11 +00:00
Gabe Black
ac5f79af28 cpu-kvm: Move the validKvmEnvironment method into KvmVM. 
This makes the generic System class consistent whether you have KVM
enabled or not.

Change-Id: Ie6928961200943d1d4e3bd129a4e4269e9f12950
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-02 01:45:58 +00:00
Giacomo Travaglini
0eba590d01 arch-arm: De-virtualize updateIntState 
De-virtualize updateIntState and replace it with the new blockIntUpdate
in the MuxingKvmGic class.

The monolithic updateIntState is GicV2 specific and it is not compatible
with the more complex IRQ update logic in GicV3, which is delegating the
update to the destributor/redistributor/cpuinterface classes

Rather than stubbing the update function the MuxingKvmGic class, we
override the blockIntUpdate to return true in case a KVM gic is in use.
This is loosening the interface, not restricting any GIC implementation
to a specific update interface/design

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ib8d9c99b720c779a2255ac47ee2a655ff281581d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55609
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-01 10:42:57 +00:00
Giacomo Travaglini
4f833b539a arch-arm: Avoid Gic write side effect with blockIntUpdate 
When trasferring the state between two GICs (essentially
writing architectural registers) an interrupt might be posted
by the model. We don't want this to happen as the GIC might
be in an inconsistent state. We therefore disable side effects
by relying on the blockIntUpdate method.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I0e5a86551705254ebacb81b7b358470faad0230c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55608
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-01 10:42:57 +00:00
Giacomo Travaglini
05d733d0cd arch-arm: Generalize KVM Gic state copying logic 
By moving the Gic state copying logic from the MuxingKvmGic to the
BaseGic we allow different Gic releases (e.g Gicv2, Gicv3) to override
the implementation accoding to their personal architectural state

It is also possible to use the same logic outside of the KVM
context

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I88d6fca69a9b61a889c5ec53221404b8396cc12d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55607
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-02-01 10:42:57 +00:00
Yu-hsin Wang
a8c85b1c40 dev-arm: Mask el2_watchdog in VExpressFastmodel platform 
el2_watchdog depends on SystemCounter. However, we have mask
system_counter in the platform. We should also mask the el2_watchdog
accordingly.

Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55306
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-01-12 08:07:43 +00:00
Yu-hsin Wang
cd9fc30d92 dev-arm: Add missing sim_objects of VExpressFastmodel 
Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55304
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-01-12 01:25:07 +00:00
Alistair Delva
75cd1ff764 dev-arm: Add RealView support for initrd/initramfs 
Update the RealView bootloader simulator to set up the initrd_addr. The
load address is derived from the dtb_addr plus the maximum allowable DTB
blob size.

Change-Id: I2eaeb1ade38d24ad8e02230cc99d12873c2f56f9
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54185
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-01-05 23:07:07 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject(). 
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-08 08:01:23 +00:00
Giacomo Travaglini
664fdd747a arch-arm, dev-arm: Add currEL function to the ISA class 
This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 18:58:49 +00:00
Giacomo Travaglini
adaab745a3 arch-arm, dev-arm: Move inSecureState helper to ISA class 
The helper function should be really part of the Arm ISA class

Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53268
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-07 18:58:49 +00:00
Gabe Black
2805f3dee1 misc: Stop including arch/pcstate.hh. 
Change-Id: Ic9ea62ae9c59fd838175fd6af4c075101d46a0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52067
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-11-30 23:30:06 +00:00
Gabe Black
636783856f dev-arm: Ensure all fields of GicV2 are initialized. 
The constructor tried to initialize all values, but in particular missed
intGroup, and may have missed other values as well.

Change-Id: Ibcd610e40259e46e3cde9b76c7f9ddc816832dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52406
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-09 21:40:58 +00:00
Gabe Black
ba5f68db3d misc: Use python 3's argumentless super(). 
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-09 13:04:44 +00:00
Gabe Black
314dae4b86 dev-arm: Set cntkctl and cnthctl in the CoreTimers constructor. 
The cntkctl and cnthctl registers were not initialized by the CoreTimers
constructor which upset valgrind when they were later used by
handleStream.

Change-Id: Iaedbb2d957aeb428fd563be2e24ccb8d2cf57f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52403
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-06 08:39:46 +00:00