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  • 28b2fee54c Fix wrong standard display. Lukas Steiner 2021-02-09 15:08:27 +01:00
  • 2143f7cbff Set payload extensions in arbiter at END_REQ. Lukas Steiner 2021-02-02 16:40:44 +01:00
  • 0e01cc5ccd Fix starvation of new arbiters. Lukas Steiner 2021-02-02 15:34:21 +01:00
  • fe144934b2 Use 1 as first payload ID. Lukas Steiner 2021-02-02 12:12:48 +01:00
  • 465bbdbe7e Add new configuration parameters for arbiter. Lukas Steiner 2021-02-02 12:08:31 +01:00
  • 28e7874a0e Fix bug in controller with ROB. Lukas Steiner 2021-02-02 12:07:52 +01:00
  • a06bd9fc5b Minor changes in arbiter. Lukas Steiner 2021-01-27 13:57:01 +01:00
  • d86dc97a28 Bugfix in fifo and reorder arbiter. Lukas Steiner 2021-01-27 13:12:36 +01:00
  • a6ce8f63cb Improve command mux for multicycle commands, RAS/CAS bus missing. Lukas Steiner 2021-01-22 15:54:37 +01:00
  • d198a78e5a Add new protocol to trace player. Lukas Steiner 2021-01-21 15:25:22 +01:00
  • 0f6611bacd Use sc_max_time() instead of SC_ZERO_TIME in all checkers. Lukas Steiner 2021-01-20 17:19:20 +01:00
  • 6c2b99a70a Fix fifo and reorder arbiter. Lukas Steiner 2021-01-20 15:29:55 +01:00
  • 0ab6562524 Add FW and BW think delay and PHY delay. Lukas Steiner 2021-01-20 14:20:44 +01:00
  • 3187c59183 Stagger refresh on different ranks. Lukas Steiner 2021-01-20 11:30:37 +01:00
  • c50b089f76 Renaming of refresh policies. Lukas Steiner 2021-01-20 09:28:06 +01:00
  • ca026981e1 Remove think delay from scheduler. Lukas Steiner 2021-01-20 08:50:15 +01:00
  • 020a01fd78 Only allow pointer to const for memspec. Lukas Steiner 2021-01-19 13:53:28 +01:00
  • aff5802a7c Increase selectable area of a transaction in Trace Analyzer. Lukas Steiner 2021-01-19 13:49:02 +01:00
  • 679d70fa65 Increase selectable area of phases with zero span. Lukas Steiner 2021-01-15 11:13:11 +01:00
  • abe8ef38b8 Implement first version of arbitration delay and think delay. Lukas Steiner 2021-01-14 16:48:21 +01:00
  • a6684d95a4 Start adaption of fifo and reorder arbiter, not finished! Lukas Steiner 2021-01-14 14:27:53 +01:00
  • 87906da06b Adapt simple arbiter and STL player to new protocol. Lukas Steiner 2021-01-14 14:27:18 +01:00
  • 772e3a2e56 Upgrade controller to new protocol. Lukas Steiner 2021-01-14 11:29:45 +01:00
  • e5e65a9323 Insert payload into scheduler after END_REQ. Lukas Steiner 2021-01-14 09:50:12 +01:00
  • 2845ebabc6 Increase time resolution in transaction tree widget. Lukas Steiner 2021-01-13 14:21:57 +01:00
  • fbf117d0a9 Include PHY delay. Lukas Steiner 2021-01-13 11:33:21 +01:00
  • c11db82a49 Merge branch 'gem5_fixes' into 'develop' Lukas Steiner 2021-01-12 11:38:33 +01:00
  • 4e967b627f Fix sqlite3 missing header file bug. Lukas Steiner 2021-01-07 16:18:08 +01:00
  • ac4566d157 Adapt gem5 paths. Lukas Steiner 2021-01-07 16:15:29 +01:00
  • 41108a269b Fix bandwidth calculation in TA. Lukas Steiner 2020-12-08 09:51:24 +01:00
  • 4aedeb8cc3 Merge branch 'power_and_buffer_analysis' into develop Lukas Steiner 2020-12-03 15:21:36 +01:00
  • ccca87d633 Corrected idle phases calculation. Lukas Steiner 2020-12-03 14:28:18 +01:00
  • e9ccfaade7 Added RR and WW Miss Matthias Jung 2020-12-02 10:00:15 +01:00
  • 9355e03012 Changed Delay Reason to RW, WR and Other Matthias Jung 2020-12-01 21:10:54 +01:00
  • a2ae5f8f49 Added bandwidth root cause analysis Matthias Jung 2020-11-30 21:40:34 +01:00
  • ea01302a12 Improved the structure of the IDLE query Matthias Jung 2020-11-30 19:17:04 +01:00
  • d15ec81677 Add idle time at the simulation start to the total idle time. Lukas Steiner 2020-11-30 16:29:44 +01:00
  • 8c19ffa2fb Merge branch 'power_and_buffer_analysis' into database_fixes Lukas Steiner 2020-11-26 14:02:05 +01:00
  • ce50dee0e2 Cleanup TLM recorder. Lukas Steiner 2020-11-26 13:57:07 +01:00
  • f008c0f4f6 Fixed a bug in memory idle calculation Matthias Jung 2020-11-25 22:03:02 +01:00
  • efdba2c9ee Merge branch 'TA_dynamic_windows' into 'develop' Lukas Steiner 2020-11-25 16:14:15 +01:00
  • 0f0eaf62bd Merge branch 'power_and_buffer_analysis' into TA_dynamic_windows Lukas Steiner 2020-11-25 15:28:59 +01:00
  • e11420cecd Change initial splitter size in TA. Lukas Steiner 2020-11-25 15:27:47 +01:00
  • 2e652deaf4 Fix checkboxes in metrics window. Lukas Steiner 2020-11-25 15:02:08 +01:00
  • 09eed96338 New delayed metric Matthias Jung 2020-11-25 11:02:48 +01:00
  • 21afa61a6b Add splitters. Lukas Steiner 2020-11-23 17:32:07 +01:00
  • 2277a6b5f9 Merge branch 'power_and_buffer_analysis' into 'develop' Lukas Steiner 2020-11-23 14:51:34 +01:00
  • e7b7653029 Some changes in analyzer Matthias Jung 2020-11-23 14:41:21 +01:00
  • 0cbe09aca1 Merge branch 'DDR5' into 'develop' Lukas Steiner 2020-11-23 13:24:44 +01:00
  • c5f89293bd Insert window bandwidth/buffer depth only when windowing is enabled. Lukas Steiner 2020-11-23 11:50:44 +01:00
  • fc3252f6ef Handle empty configuration files. Lukas Steiner 2020-11-13 10:57:48 +01:00
  • 362ca31303 Use uint64_t for number of lines in trace player. Lukas Steiner 2020-11-13 09:01:05 +01:00
  • 981637188f Added Power Analysis in Trace Analyzer Matthias Jung 2020-11-11 10:06:01 +01:00
  • 7bba11e047 Move initial SQL table into source file. Lukas Steiner 2020-11-11 09:52:34 +01:00
  • 3be2d9f56b Include average bandwidth windowing. Lukas Steiner 2020-11-11 09:51:31 +01:00
  • ed8ee0ec06 Merge branch 'rambus_scheduler' into DDR5 Lukas Steiner 2020-11-04 16:50:06 +01:00
  • ccf686baf6 Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler Lukas Steiner 2020-11-04 16:48:31 +01:00
  • fe53143f64 Merge branch 'rambus_scheduler' into DDR5 Lukas Steiner 2020-11-04 16:04:25 +01:00
  • 7d7dba4c68 Reset simulator config. Lukas Steiner 2020-11-04 16:03:49 +01:00
  • cc3a7a617b Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler Lukas Steiner 2020-11-04 15:58:55 +01:00
  • d723306130 Merge branch 'rambus_scheduler' into DDR5 Lukas Steiner 2020-11-04 15:56:26 +01:00
  • 6108c6ca93 Add max buffer depth to general info table. Lukas Steiner 2020-11-04 15:46:08 +01:00
  • 5b4f5e0c74 Added Queue Analysis Plot Matthias Jung 2020-11-04 15:36:13 +01:00
  • d7409542a1 Add simple arbiter. Lukas Steiner 2020-11-04 15:26:51 +01:00
  • d85790ad63 Add shared scheduler buffer counter. Lukas Steiner 2020-11-04 13:26:28 +01:00
  • 0fec34240d Add scheduler buffer depth recording. Lukas Steiner 2020-11-04 11:15:22 +01:00
  • e5d340a603 Merge branch 'rambus_scheduler' into DDR5. Lukas Steiner 2020-11-03 15:13:19 +01:00
  • 11bfed8b6a Finished Latency Analysis Tool in TA Matthias Jung 2020-11-02 19:53:53 +01:00
  • 9315cd1345 Set payload IDs at correct time. Lukas Steiner 2020-10-28 11:59:09 +01:00
  • d2878c62f2 Add reorder arbiter. Lukas Steiner 2020-10-28 11:18:13 +01:00
  • c744c43ab2 Added first latency analysis Matthias Jung 2020-10-27 21:29:39 +01:00
  • fe1d8eafdd Code cleanup. Lukas Steiner 2020-10-27 16:41:00 +01:00
  • 2d507fb327 Decrement active transactions after BEGIN_RESP. Lukas Steiner 2020-10-27 16:16:48 +01:00
  • f6752cb09a Improved arbiter with thread and channel queues. Lukas Steiner 2020-10-27 16:02:11 +01:00
  • ac670f2ea7 Merge branch 'rambus_scheduler' into DDR5 Lukas Steiner 2020-10-27 10:04:15 +01:00
  • 5d6042a16a Renaming of payload IDs in arbiter. Lukas Steiner 2020-10-27 09:57:48 +01:00
  • 2c7f555172 Add threadPayloadID. Lukas Steiner 2020-10-26 14:36:35 +01:00
  • baf2440a4d Change payloadID to channelPayloadID. Lukas Steiner 2020-10-26 14:15:06 +01:00
  • b70c3351d3 Prepare arbiter for reorder buffer. Lukas Steiner 2020-10-26 13:54:11 +01:00
  • 3af9159b44 Missing cmake changes. Lukas Steiner 2020-10-26 09:10:35 +01:00
  • ffca62be70 Renaming scheduler buffer to buffer counter. Lukas Steiner 2020-10-26 09:05:50 +01:00
  • 11ec4036ee Merge branch 'rambus_scheduler' into DDR5 Lukas Steiner 2020-10-26 08:37:59 +01:00
  • e26a438d06 Code formatting. Lukas Steiner 2020-10-23 15:04:40 +02:00
  • 7bab23f80e Move methods from config to memspec. Lukas Steiner 2020-10-23 15:00:49 +02:00
  • bfb5f16563 Move getSimMemSizeInBytes to memspec. Lukas Steiner 2020-10-23 14:24:32 +02:00
  • 65d148b7a7 Improved configuration process. Lukas Steiner 2020-10-23 12:07:30 +02:00
  • 472c810f89 Add separate scheduler buffers (bankwise, separate read/write). Lukas Steiner 2020-10-22 16:41:49 +02:00
  • f95a35e9e8 Merge branch 'develop' into DDR5 Lukas Steiner 2020-10-22 14:10:24 +02:00
  • 27819b4a7b Merge branch 'cpp_speedups' into 'develop' Lukas Steiner 2020-10-22 14:05:38 +02:00
  • 32c7148dd9 Set correct time of generation in arbiter. Lukas Steiner 2020-10-22 13:43:00 +02:00
  • 24b46811c0 Bugfix rank-to-rank dependencies. Lukas Steiner 2020-10-20 14:29:28 +02:00
  • 328a371843 Make controller easier to understand. Lukas Steiner 2020-10-20 09:32:28 +02:00
  • 0501bbd2c8 Add trace generator cpp file. Lukas Steiner 2020-10-08 16:00:52 +02:00
  • e90df2174c Directly call arbiter PEQ from trace player. Lukas Steiner 2020-10-08 14:42:00 +02:00
  • 432d37a9d7 File cleanup. Lukas Steiner 2020-10-06 15:51:24 +02:00
  • d40462dcf7 Split up StlPlayer into source and header file. Lukas Steiner 2020-10-06 13:33:50 +02:00
  • c79de8ac03 Fix wrong DDR5 timing dependencies. Lukas Steiner 2020-10-05 16:06:06 +02:00
  • 0e06c54917 Add more DDR5 memspecs. Lukas Steiner 2020-10-05 14:11:56 +02:00
  • 280a0b5f66 Set ddr5 example as default. Lukas Steiner 2020-10-02 16:28:05 +02:00
  • 6a8ce57d08 Add selection of fine granularity refresh mode. Lukas Steiner 2020-10-02 16:12:14 +02:00