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Move getSimMemSizeInBytes to memspec.

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This commit is contained in:
Lukas Steiner
2020-10-23 14:24:32 +02:00
parent 65d148b7a7
commit bfb5f16563
23 changed files with 239 additions and 42 deletions
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38
DRAMSys/library/src/configuration/Configuration.cpp
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@@ -258,44 +258,6 @@ void Configuration::setPathToResources(std::string path)
temperatureSim.setPathToResources(path);
}
// Returns the total memory size in bytes
std::uint64_t Configuration::getSimMemSizeInBytes()
{
// 1. Get number of banks, rows, columns and data width in bits for one die (or chip)
//std::string type = memSpec->memoryType;
std::uint64_t ranks = memSpec->numberOfRanks;
std::uint64_t bankgroups = memSpec->numberOfBankGroups;
std::uint64_t banks = memSpec->numberOfBanks;
std::uint64_t rows = memSpec->numberOfRows;
std::uint64_t columns = memSpec->numberOfColumns;
std::uint64_t bitWidth = memSpec->bitWidth;
std::uint64_t devicesOnDIMM = memSpec->numberOfDevicesOnDIMM;
// 2. Calculate size of one DRAM chip in bits
std::uint64_t chipBitSize = banks * rows * columns * bitWidth;
// 3. Calculate size of one DRAM chip in bytes
std::uint64_t chipSize = chipBitSize / 8;
// 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM)
std::uint64_t memorySize = chipSize * memSpec->numberOfDevicesOnDIMM;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "dummy" << std::endl;
std::cout << " Memory size in bytes: " << memorySize << std::endl;
std::cout << " Number of ranks: " << ranks << std::endl;
std::cout << " Number of bankgroups: " << bankgroups << std::endl;
std::cout << " Number of banks: " << banks << std::endl;
std::cout << " Number of rows: " << rows << std::endl;
std::cout << " Number of columns: " << columns << std::endl;
std::cout << " Chip data bus width: " << bitWidth << std::endl;
std::cout << " Chip size in bits: " << chipBitSize << std::endl;
std::cout << " Chip Size in bytes: " << chipSize << std::endl;
std::cout << " Devices/Chips on DIMM: " << devicesOnDIMM << std::endl;
std::cout << std::endl;
assert(memorySize > 0);
return memorySize;
}
// Returns the width of the data bus.
// All DRAM chips on a DIMM operate in lockstep,
// which constituing aggregate data bus width = chip's bus width * # locksteep-operated chips

1
DRAMSys/library/src/configuration/Configuration.h
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@@ -110,7 +110,6 @@ public:
// Temperature Simulation related
TemperatureSimConfig temperatureSim;
std::uint64_t getSimMemSizeInBytes();
unsigned int getDataBusWidth();
unsigned int getBytesPerBurst();
unsigned int adjustNumBytesAfterECC(unsigned bytes);

3
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -43,7 +43,8 @@
using namespace tlm;
using json = nlohmann::json;
MemSpec::MemSpec(json &memspec, MemoryType memoryType, unsigned numberOfChannels,
MemSpec::MemSpec(json &memspec, MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups,

5
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -79,8 +79,11 @@ public:
sc_time getCommandLength(Command) const;
virtual uint64_t getSimMemSizeInBytes() const = 0;
protected:
MemSpec(nlohmann::json &memspec, MemoryType memoryType, unsigned numberOfChannels,
MemSpec(nlohmann::json &memspec, MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups,

24
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
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@@ -138,3 +138,27 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecDDR3::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "DDR3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices on DIMM: " << numberOfDevicesOnDIMM << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
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@@ -92,6 +92,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECDDR3_H

25
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
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@@ -155,3 +155,28 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecDDR4::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfDevicesOnDIMM * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "DDR4" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices on DIMM: " << numberOfDevicesOnDIMM << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
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@@ -98,6 +98,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECDDR4_H

24
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
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@@ -142,3 +142,27 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecGDDR5::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
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@@ -90,6 +90,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECGDDR5_H

24
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
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@@ -142,3 +142,27 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecGDDR5X::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5X" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
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@@ -90,6 +90,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECGDDR5X_H

24
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
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@@ -144,3 +144,27 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecGDDR6::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR6" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
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@@ -92,6 +92,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECGDDR6_H

24
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
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@@ -139,3 +139,27 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecHBM2::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "HBM2" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
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@@ -85,6 +85,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECHBM2_H

23
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -147,3 +147,26 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const
}
}
uint64_t MemSpecLPDDR4::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
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@@ -85,6 +85,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECLPDDR4_H

23
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
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@@ -146,3 +146,26 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecWideIO::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
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@@ -98,6 +98,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECWIDEIO_H

23
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
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@@ -131,3 +131,26 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const
return TimeInterval();
}
}
uint64_t MemSpecWideIO2::getSimMemSizeInBytes() const
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
uint64_t memorySizeBytes = deviceSizeBytes * numberOfRanks;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Ranks: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
assert(memorySizeBytes > 0);
return memorySizeBytes;
}

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
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@@ -79,6 +79,8 @@ public:
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
virtual uint64_t getSimMemSizeInBytes() const override;
};
#endif // MEMSPECWIDEIO2_H

2
DRAMSys/library/src/simulation/dram/Dram.cpp
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@@ -71,7 +71,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
storeMode = config.storeMode;
uint64_t memorySize = config.getSimMemSizeInBytes();
uint64_t memorySize = config.memSpec->getSimMemSizeInBytes();
if (storeMode == Configuration::StoreMode::Store)
{
if (config.useMalloc)