Fix wrong DDR5 timing dependencies.
This commit is contained in:
@@ -300,6 +300,12 @@ void Controller::controllerMethod()
|
||||
for (auto it : bankMachinesOnRank[rank.ID()])
|
||||
it->updateState(command);
|
||||
}
|
||||
else if (isGroupCommand(command))
|
||||
{
|
||||
for (unsigned bankID = (bank.ID() % memSpec->banksPerGroup);
|
||||
bankID < memSpec->banksPerRank; bankID += memSpec->banksPerGroup)
|
||||
bankMachinesOnRank[rank.ID()][bankID]->updateState(command);
|
||||
}
|
||||
else
|
||||
bankMachines[bank.ID()]->updateState(command);
|
||||
|
||||
|
||||
@@ -53,6 +53,7 @@ CheckerDDR5::CheckerDDR5()
|
||||
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks));
|
||||
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands());
|
||||
|
||||
// Required for Same Bank Refresh
|
||||
lastScheduledByCommandAndBankInGroup = std::vector<std::vector<sc_time>>
|
||||
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks * memSpec->banksPerGroup));
|
||||
|
||||
@@ -86,7 +87,7 @@ CheckerDDR5::CheckerDDR5()
|
||||
tWRPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset;
|
||||
tWRAPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset;
|
||||
|
||||
// TODO: tRTP BL 32!!! (check LPDDR4)
|
||||
// TODO: tRTP BL 32 (similar to LPDDR4)
|
||||
}
|
||||
|
||||
sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -98,7 +99,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
Rank physicalrank = Rank(logicalrank.ID() / memSpec->logicalRanksPerPhysicalRank);
|
||||
Rank dimmrank = Rank(physicalrank.ID() / memSpec->physicalRanksPerDIMMRank);
|
||||
|
||||
unsigned bankInGroupID = rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup;
|
||||
Bank bankInGroup = Bank(rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup);
|
||||
|
||||
if (command == Command::RD || command == Command::RDA)
|
||||
{
|
||||
@@ -205,7 +206,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -313,7 +314,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdOffset);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRESB][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRESB][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - cmdOffset);
|
||||
|
||||
@@ -323,7 +324,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
|
||||
// TODO: No tRFC_dlr and tRFC_dpr between REFA and ACT?
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::REFSB][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::REFSB][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCsb_slr - cmdOffset);
|
||||
|
||||
@@ -405,23 +406,23 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
}
|
||||
else if (command == Command::PRESB)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RD][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RD][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WR][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WR][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK);
|
||||
|
||||
@@ -469,12 +470,12 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC_dpr);
|
||||
|
||||
// REFSB tRFCsb
|
||||
// REFSB tRFCsb_slr/dlr
|
||||
// PRESB tRP
|
||||
}
|
||||
else if (command == Command::REFSB)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
|
||||
|
||||
@@ -482,21 +483,21 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + memSpec->tCK);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRE][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRE][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
|
||||
|
||||
// PREA tRP
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRESB][bankInGroupID];
|
||||
lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRESB][bankInGroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user