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Add more DDR5 memspecs.

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This commit is contained in:
Lukas Steiner
2020-10-05 14:11:56 +02:00
parent 280a0b5f66
commit 0e06c54917
9 changed files with 613 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json
View File

@@ -17,7 +17,7 @@
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 22,
@@ -33,41 +33,41 @@
"WPRE": 2,
"WPST": 0,
"WR": 48,
"CCD_L_slr": 8,
"CCD_L_slr": 8,
"CCD_L_WR_slr": 32,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 8,
"CCD_WR_dlr": 8,
"CCD_WR_dpr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 8,
"RRD_S_slr": 8,
"RRD_dlr": 4,
"FAW_slr": 32,
"FAW_dlr": 16,
"WTR_L": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,
"RFC1_dlr": 104,
"RFC2_dlr": 70,
"RFC1_dpr": 104,
"RFC2_dpr": 70,
"RFCsb_slr": 184,
"RFCsb_dlr": 62,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 16,
"WTR_S": 4,
"RFC1_slr": 312,
"RFC2_slr": 208,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 184,
"RFCsb_dlr": 0,
"REFI1": 6240,
"REFI2": 3120,
"REFI2": 3120,
"REFISB": 1560,
"REFSBRD_slr": 48,
"REFSBRD_dlr": 24,
"RTRS": 2,
"CPDED": 8,
"PD": 12,
"XP": 12,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFSBRD_slr": 48,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 8,
"PD": 12,
"XP": 12,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 1600
}
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 26,
"PPD": 2,
"RP": 26,
"RAS": 58,
"RL": 26,
"RTP": 14,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 24,
"WPRE": 2,
"WPST": 0,
"WR": 54,
"CCD_L_slr": 9,
"CCD_L_WR_slr": 36,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 9,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 18,
"WTR_S": 5,
"RFC1_slr": 351,
"RFC2_slr": 234,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 207,
"RFCsb_dlr": 0,
"REFI1": 7020,
"REFI2": 3510,
"REFISB": 1755,
"REFSBRD_slr": 54,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 9,
"PD": 14,
"XP": 14,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 1800
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 28,
"PPD": 2,
"RP": 28,
"RAS": 64,
"RL": 28,
"RTP": 15,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 26,
"WPRE": 2,
"WPST": 0,
"WR": 60,
"CCD_L_slr": 10,
"CCD_L_WR_slr": 40,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 10,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 20,
"WTR_S": 5,
"RFC1_slr": 390,
"RFC2_slr": 260,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 230,
"RFCsb_dlr": 0,
"REFI1": 7800,
"REFI2": 3900,
"REFISB": 1950,
"REFSBRD_slr": 60,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 10,
"PD": 15,
"XP": 15,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 2000
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 32,
"PPD": 2,
"RP": 32,
"RAS": 71,
"RL": 32,
"RTP": 17,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 30,
"WPRE": 2,
"WPST": 0,
"WR": 66,
"CCD_L_slr": 11,
"CCD_L_WR_slr": 44,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 11,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 22,
"WTR_S": 6,
"RFC_slr": 429,
"RFC_slr": 286,
"RFC_dlr": 0,
"RFC_dlr": 0,
"RFC_dpr": 0,
"RFC_dpr": 0,
"RFCsb_slr": 253,
"RFCsb_dlr": 0,
"REFI1": 8580,
"REFI2": 4290,
"REFISB": 2145,
"REFSBRD_slr": 66,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 11,
"PD": 17,
"XP": 17,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 2200
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 34,
"PPD": 2,
"RP": 34,
"RAS": 77,
"RL": 34,
"RTP": 18,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 32,
"WPRE": 2,
"WPST": 0,
"WR": 72,
"CCD_L_slr": 12,
"CCD_L_WR_slr": 48,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 12,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 24,
"WTR_S": 6,
"RFC1_slr": 468,
"RFC2_slr": 312,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 276,
"RFCsb_dlr": 0,
"REFI1": 9360,
"REFI2": 4680,
"REFISB": 2340,
"REFSBRD_slr": 72,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 12,
"PD": 18,
"XP": 18,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 2400
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 38,
"PPD": 2,
"RP": 38,
"RAS": 84,
"RL": 38,
"RTP": 20,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 36,
"WPRE": 2,
"WPST": 0,
"WR": 78,
"CCD_L_slr": 13,
"CCD_L_WR_slr": 52,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 13,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 26,
"WTR_S": 7,
"RFC1_slr": 507,
"RFC2_slr": 338,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 299,
"RFCsb_dlr": 0,
"REFI1": 10140,
"REFI2": 5070,
"REFISB": 2535,
"REFSBRD_slr": 78,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 13,
"PD": 20,
"XP": 20,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 2600
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 40,
"PPD": 2,
"RP": 40,
"RAS": 90,
"RL": 40,
"RTP": 21,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 38,
"WPRE": 2,
"WPST": 0,
"WR": 84,
"CCD_L_slr": 14,
"CCD_L_WR_slr": 56,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 14,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 28,
"WTR_S": 7,
"RFC1_slr": 546,
"RFC2_slr": 364,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 322,
"RFCsb_dlr": 0,
"REFI1": 10920,
"REFI2": 5460,
"REFISB": 2730,
"REFSBRD_slr": 84,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 14,
"PD": 21,
"XP": 21,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 2800
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 42,
"PPD": 2,
"RP": 42,
"RAS": 96,
"RL": 42,
"RTP": 23,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 40,
"WPRE": 2,
"WPST": 0,
"WR": 90,
"CCD_L_slr": 15,
"CCD_L_WR_slr": 60,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 15,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 30,
"WTR_S": 8,
"RFC1_slr": 585,
"RFC2_slr": 390,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 345,
"RFCsb_dlr": 0,
"REFI1": 11700,
"REFI2": 5850,
"REFISB": 2925,
"REFSBRD_slr": 90,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 15,
"PD": 23,
"XP": 23,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 3000
}
}
}

73
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json Normal file
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@@ -0,0 +1,73 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBankGroups": 8,
"nbrOfBanks": 16,
"nbrOfColumns": 2048,
"nbrOfRanks": 1,
"nbrOfDIMMRanks": 1,
"nbrOfPhysicalRanks": 1,
"nbrOfLogicalRanks": 1,
"nbrOfRows": 65536,
"width": 4,
"nbrOfDevicesOnDIMM": 8,
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A",
"memoryType": "DDR5",
"memtimingspec": {
"RCD": 46,
"PPD": 2,
"RP": 46,
"RAS": 103,
"RL": 46,
"RTP": 24,
"RPRE": 1,
"RPST": 0,
"RDDQS": 0,
"WL": 44,
"WPRE": 2,
"WPST": 0,
"WR": 96,
"CCD_L_slr": 16,
"CCD_L_WR_slr": 64,
"CCD_S_slr": 8,
"CCD_S_WR_slr": 8,
"CCD_dlr": 0,
"CCD_WR_dlr": 0,
"CCD_WR_dpr": 0,
"RRD_L_slr": 16,
"RRD_S_slr": 8,
"RRD_dlr": 0,
"FAW_slr": 32,
"FAW_dlr": 0,
"WTR_L": 32,
"WTR_S": 8,
"RFC1_slr": 624,
"RFC2_slr": 416,
"RFC1_dlr": 0,
"RFC2_dlr": 0,
"RFC1_dpr": 0,
"RFC2_dpr": 0,
"RFCsb_slr": 368,
"RFCsb_dlr": 0,
"REFI1": 12480,
"REFI2": 6240,
"REFISB": 3120,
"REFSBRD_slr": 96,
"REFSBRD_dlr": 0,
"RTRS": 2,
"CPDED": 16,
"PD": 24,
"XP": 24,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"clkMhz": 3200
}
}
}