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Add scheduler buffer depth recording.

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This commit is contained in:
Lukas Steiner
2020-11-04 11:15:22 +01:00
parent 9315cd1345
commit 0fec34240d
18 changed files with 124 additions and 23 deletions
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8
DRAMSys/library/resources/scripts/createTraceDB.sql
View File

@@ -6,6 +6,7 @@ DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
DROP TABLE IF EXISTS BufferDepth;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
@@ -54,6 +55,11 @@ CREATE TABLE Power(
AveragePower DOUBLE
);
CREATE TABLE BufferDepth(
Time DOUBLE,
BufferNumber INTEGER,
AverageBufferDepth DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
@@ -87,7 +93,7 @@ CREATE TABLE Transactions(
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);

15
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -80,6 +80,7 @@ TlmRecorder::~TlmRecorder()
sqlite3_finalize(insertDebugMessageStatement);
sqlite3_finalize(updateDataStrobeStatement);
sqlite3_finalize(insertPowerStatement);
sqlite3_finalize(insertBufferDepthStatement);
}
void TlmRecorder::recordPower(double timeInSeconds, double averagePower)
@@ -89,6 +90,17 @@ void TlmRecorder::recordPower(double timeInSeconds, double averagePower)
executeSqlStatement(insertPowerStatement);
}
void TlmRecorder::recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth)
{
for (size_t index = 0; index < averageBufferDepth.size(); index++)
{
sqlite3_bind_double(insertBufferDepthStatement, 1, timeInSeconds);
sqlite3_bind_int(insertBufferDepthStatement, 2, index);
sqlite3_bind_double(insertBufferDepthStatement, 3, averageBufferDepth[index]);
executeSqlStatement(insertBufferDepthStatement);
}
}
void TlmRecorder::recordPhase(tlm_generic_payload &trans,
tlm_phase phase, sc_time time)
{
@@ -294,6 +306,7 @@ void TlmRecorder::prepareSqlStatements()
insertDebugMessageString =
"INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)";
insertBufferDepthString = "INSERT INTO BufferDepth VALUES (:time,:bufferNumber,:averageBufferDepth)";
sqlite3_prepare_v2(db, insertTransactionString.c_str(), -1,
&insertTransactionStatement, 0);
@@ -310,6 +323,7 @@ void TlmRecorder::prepareSqlStatements()
sqlite3_prepare_v2(db, insertDebugMessageString.c_str(), -1,
&insertDebugMessageStatement, 0);
sqlite3_prepare_v2(db, insertPowerString.c_str(), -1, &insertPowerStatement, 0);
sqlite3_prepare_v2(db, insertBufferDepthString.c_str(), -1, &insertBufferDepthStatement, 0);
}
void TlmRecorder::insertDebugMessageInDB(std::string message, const sc_time &time)
@@ -411,7 +425,6 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData)
recordingData.cmd.c_str(), recordingData.cmd.length(), NULL);
executeSqlStatement(insertTransactionStatement);
}
void TlmRecorder::insertRangeInDB(unsigned int id, const sc_time &begin,

10
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -77,13 +77,15 @@ public:
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase,
sc_time time);
void recordPower(double timeInSeconds, double averagePower);
void recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth);
void recordDebugMessage(std::string message, sc_time time);
void updateDataStrobe(const sc_time &begin, const sc_time &end,
tlm::tlm_generic_payload &trans);
void closeConnection();
private:
struct Transaction {
struct Transaction
{
Transaction() {}
Transaction(unsigned int id): id(id) {}
@@ -142,10 +144,12 @@ private:
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement,
*updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement,
*insertGeneralInfoStatement, *insertCommandLengthsStatement,
*insertDebugMessageStatement, *updateDataStrobeStatement, *insertPowerStatement;
*insertDebugMessageStatement, *updateDataStrobeStatement,
*insertPowerStatement, *insertBufferDepthStatement;
std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString,
updatePhaseString, insertGeneralInfoString, insertCommandLengthsString,
insertDebugMessageString, updateDataStrobeString, insertPowerString;
insertDebugMessageString, updateDataStrobeString, insertPowerString,
insertBufferDepthString;
};
#endif // TLMRECORDER_H

7
DRAMSys/library/src/controller/Controller.h
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@@ -62,7 +62,7 @@ class Controller : public ControllerIF
public:
Controller(sc_module_name);
SC_HAS_PROCESS(Controller);
virtual ~Controller();
virtual ~Controller() override;
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
@@ -72,6 +72,9 @@ protected:
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase);
virtual void sendToDram(Command, tlm::tlm_generic_payload *);
virtual void controllerMethod();
SchedulerIF *scheduler;
MemSpec *memSpec;
private:
@@ -82,7 +85,6 @@ private:
std::vector<BankMachine *> bankMachines;
std::vector<std::vector<BankMachine *>> bankMachinesOnRank;
CmdMuxIF *cmdMux;
SchedulerIF *scheduler;
CheckerIF *checker;
RespQueueIF *respQueue;
std::vector<RefreshManagerIF *> refreshManagers;
@@ -99,7 +101,6 @@ private:
void startBeginResp();
void finishEndResp();
void controllerMethod();
sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
};

35
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -37,6 +37,15 @@
using namespace tlm;
ControllerRecordable::ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder)
: Controller(name), tlmRecorder(tlmRecorder)
{
sensitive << bufferDepthWindowEvent;
bufferDepthWindowSize = Configuration::getInstance().windowSize * memSpec->tCK;
slidingAverageBufferDepth = std::vector<sc_time>(scheduler->getBufferDepth().size());
averageBufferDepth = std::vector<double>(scheduler->getBufferDepth().size());
}
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{
@@ -90,3 +99,29 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha
tlmRecorder->recordPhase(trans, phase, recTime);
}
void ControllerRecordable::controllerMethod()
{
sc_time timeDiff = sc_time_stamp() - lastTimeCalled;
const std::vector<unsigned> &bufferDepth = scheduler->getBufferDepth();
for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
slidingAverageBufferDepth[index] += bufferDepth[index] * timeDiff;
lastTimeCalled = sc_time_stamp();
if (sc_time_stamp() % bufferDepthWindowSize == SC_ZERO_TIME && timeDiff != SC_ZERO_TIME)
{
bufferDepthWindowEvent.notify(bufferDepthWindowSize);
for (size_t index = 0; index < slidingAverageBufferDepth.size(); index++)
{
averageBufferDepth[index] = slidingAverageBufferDepth[index] / bufferDepthWindowSize;
slidingAverageBufferDepth[index] = SC_ZERO_TIME;
}
tlmRecorder->recordBufferDepth(sc_time_stamp().to_seconds(), averageBufferDepth);
}
Controller::controllerMethod();
}

12
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -41,8 +41,8 @@
class ControllerRecordable final : public Controller
{
public:
ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) :
Controller(name), tlmRecorder(tlmRecorder) {}
ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder);
virtual ~ControllerRecordable() override {}
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
@@ -53,9 +53,17 @@ protected:
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase) override;
virtual void sendToDram(Command, tlm::tlm_generic_payload *) override;
virtual void controllerMethod() override;
private:
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;
sc_event bufferDepthWindowEvent;
sc_time bufferDepthWindowSize;
std::vector<sc_time> slidingAverageBufferDepth;
std::vector<double> averageBufferDepth;
sc_time lastTimeCalled = SC_ZERO_TIME;
};
#endif // CONTROLLERRECORDABLE_H

13
DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.cpp
View File

@@ -38,21 +38,26 @@
BufferCounterBankwise::BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks)
: requestBufferSize(requestBufferSize)
{
requestsOnBank = std::vector<unsigned>(numberOfBanks, 0);
numRequestsOnBank = std::vector<unsigned>(numberOfBanks, 0);
}
bool BufferCounterBankwise::hasBufferSpace() const
{
return (requestsOnBank[lastBankID] < requestBufferSize);
return (numRequestsOnBank[lastBankID] < requestBufferSize);
}
void BufferCounterBankwise::storeRequest(tlm::tlm_generic_payload *payload)
{
lastBankID = DramExtension::getBank(payload).ID();
requestsOnBank[lastBankID]++;
numRequestsOnBank[lastBankID]++;
}
void BufferCounterBankwise::removeRequest(tlm::tlm_generic_payload *payload)
{
requestsOnBank[DramExtension::getBank(payload).ID()]--;
numRequestsOnBank[DramExtension::getBank(payload).ID()]--;
}
const std::vector<unsigned> &BufferCounterBankwise::getBufferDepth() const
{
return numRequestsOnBank;
}

3
DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h
View File

@@ -46,10 +46,11 @@ public:
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *payload) override;
virtual void removeRequest(tlm::tlm_generic_payload *payload) override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
private:
const unsigned requestBufferSize;
std::vector<unsigned> requestsOnBank;
std::vector<unsigned> numRequestsOnBank;
unsigned lastBankID;
};

1
DRAMSys/library/src/controller/scheduler/BufferCounterIF.h
View File

@@ -43,6 +43,7 @@ public:
virtual bool hasBufferSpace() const = 0;
virtual void storeRequest(tlm::tlm_generic_payload *payload) = 0;
virtual void removeRequest(tlm::tlm_generic_payload *payload) = 0;
virtual const std::vector<unsigned> &getBufferDepth() const = 0;
};
#endif // BUFFERCOUNTERIF_H

20
DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.cpp
View File

@@ -35,25 +35,33 @@
#include "BufferCounterReadWrite.h"
BufferCounterReadWrite::BufferCounterReadWrite(unsigned requestBufferSize)
: requestBufferSize(requestBufferSize) {}
: requestBufferSize(requestBufferSize)
{
numReadWriteRequests = std::vector<unsigned>(2);
}
bool BufferCounterReadWrite::hasBufferSpace() const
{
return (numberOfReads < requestBufferSize && numberOfWrites < requestBufferSize);
return (numReadWriteRequests[0] < requestBufferSize && numReadWriteRequests[1] < requestBufferSize);
}
void BufferCounterReadWrite::storeRequest(tlm::tlm_generic_payload *payload)
{
if (payload->is_read())
numberOfReads++;
numReadWriteRequests[0]++;
else
numberOfWrites++;
numReadWriteRequests[1]++;
}
void BufferCounterReadWrite::removeRequest(tlm::tlm_generic_payload *payload)
{
if (payload->is_read())
numberOfReads--;
numReadWriteRequests[0]--;
else
numberOfWrites--;
numReadWriteRequests[1]--;
}
const std::vector<unsigned> &BufferCounterReadWrite::getBufferDepth() const
{
return numReadWriteRequests;
}

4
DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h
View File

@@ -44,11 +44,11 @@ public:
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *payload) override;
virtual void removeRequest(tlm::tlm_generic_payload *payload) override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
private:
const unsigned requestBufferSize;
unsigned numberOfReads = 0;
unsigned numberOfWrites = 0;
std::vector<unsigned> numReadWriteRequests;
};
#endif // BUFFERCOUNTERREADWRITE_H

5
DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
View File

@@ -94,3 +94,8 @@ bool SchedulerFifo::hasFurtherRequest(Bank bank) const
else
return false;
}
const std::vector<unsigned> &SchedulerFifo::getBufferDepth() const
{
return bufferCounter->getBufferDepth();
}

1
DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
View File

@@ -54,6 +54,7 @@ public:
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::deque<tlm::tlm_generic_payload *>> buffer;

5
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -115,3 +115,8 @@ bool SchedulerFrFcfs::hasFurtherRequest(Bank bank) const
{
return (buffer[bank.ID()].size() >= 2);
}
const std::vector<unsigned> &SchedulerFrFcfs::getBufferDepth() const
{
return bufferCounter->getBufferDepth();
}

1
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -54,6 +54,7 @@ public:
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;

5
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -143,3 +143,8 @@ bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank) const
else
return false;
}
const std::vector<unsigned> &SchedulerFrFcfsGrp::getBufferDepth() const
{
return bufferCounter->getBufferDepth();
}

1
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -54,6 +54,7 @@ public:
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;

1
DRAMSys/library/src/controller/scheduler/SchedulerIF.h
View File

@@ -52,6 +52,7 @@ public:
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const = 0;
virtual bool hasFurtherRowHit(Bank, Row) const = 0;
virtual bool hasFurtherRequest(Bank) const = 0;
virtual const std::vector<unsigned> &getBufferDepth() const = 0;
};
#endif // SCHEDULERIF_H