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Fix bandwidth calculation in TA.

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This commit is contained in:
Lukas Steiner
2020-12-08 09:51:24 +01:00
parent 4aedeb8cc3
commit 41108a269b
1 changed files with 6 additions and 8 deletions
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14
DRAMSys/traceAnalyzer/scripts/memUtil.py
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@@ -64,16 +64,14 @@ def getWindowSize(connection):
def maximum_data_rate(connection):
memspec = MemSpec(connection)
memoryType = memspec.getValue("memoryType")
if (memoryType.find("DDR") != -1):
width = 64
else:
if (memoryType.find("WIDEIO") != -1):
width = memspec.getValue("width")
memspec = MemSpec(connection)
try:
width = memspec.getIntValue("memarchitecturespec", "nbrOfDevicesOnDIMM") * memspec.getIntValue("memarchitecturespec", "width")
except:
width = memspec.getIntValue("memarchitecturespec", "width")
clk = memspec.getIntValue("memtimingspec", "clkMhz")
rate = memspec.getIntValue("memarchitecturespec", "dataRate")
maxDataRate = float(clk)*float(width)*float(rate)
maxDataRate = float(clk) * float(width) * float(rate)
return maxDataRate