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Include PHY delay.

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This commit is contained in:
Lukas Steiner
2021-01-13 11:33:21 +01:00
parent c11db82a49
commit fbf117d0a9
19 changed files with 60 additions and 55 deletions
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6
DRAMSys/library/src/configuration/Configuration.cpp
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@@ -181,6 +181,12 @@ void Configuration::setParameter(std::string name, nlohmann::json value)
powerDownTimeout = value;
else if (name == "MaxActiveTransactions")
maxActiveTransactions = value;
else if (name == "ArbitrationDelay")
arbitrationDelay = memSpec->tCK * value;
else if (name == "ThinkDelay")
thinkDelay = memSpec->tCK * value;
else if (name == "PhyDelay")
phyDelay = memSpec->tCK * value;
//SimConfig------------------------------------------------
else if (name == "SimulationName")
simulationName = value;

4
DRAMSys/library/src/configuration/Configuration.h
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@@ -82,6 +82,9 @@ public:
enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy;
unsigned int powerDownTimeout = 3;
unsigned int maxActiveTransactions = 64;
sc_time arbitrationDelay = SC_ZERO_TIME;
sc_time thinkDelay = SC_ZERO_TIME;
sc_time phyDelay = SC_ZERO_TIME;
// SimConfig
std::string simulationName = "default";
@@ -95,7 +98,6 @@ public:
bool checkTLM2Protocol = false;
enum class ECCMode {Disabled, Hamming} eccMode;
ECCBaseClass *pECC = nullptr;
bool gem5 = false;
bool useMalloc = false;
unsigned long long int addressOffset = 0;

4
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
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@@ -123,9 +123,9 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration);
return TimeInterval(tRL, tRL + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration);
return TimeInterval(tWL, tWL + burstDuration);
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");

4
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
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@@ -142,9 +142,9 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration);
return TimeInterval(tRL, tRL + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration);
return TimeInterval(tWL, tWL + burstDuration);
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");

4
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
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@@ -185,9 +185,9 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + cmdOffset_L, sc_time_stamp() + tRL + burstDuration + cmdOffset_L);
return TimeInterval(tRL + cmdOffset_L, tRL + burstDuration + cmdOffset_L);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + cmdOffset_L, sc_time_stamp() + tWL + burstDuration + cmdOffset_L);
return TimeInterval(tWL + cmdOffset_L, tWL + burstDuration + cmdOffset_L);
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -131,11 +131,11 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
else
{
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -131,11 +131,11 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
else
{
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -133,11 +133,11 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
else
{
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");

6
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -128,11 +128,9 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tDQSCK,
sc_time_stamp() + tRL + tDQSCK + burstDuration);
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL,
sc_time_stamp() + tWL + burstDuration);
return TimeInterval(tWL, tWL + burstDuration);
else
{
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");

8
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -135,11 +135,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * tCK,
sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * tCK);
return TimeInterval(tRL + tDQSCK + 3 * tCK,
tRL + tDQSCK + burstDuration + 3 * tCK);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * tCK,
sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK,
tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
else
{
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -129,11 +129,9 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tAC,
sc_time_stamp() + tRL + tAC + burstDuration);
return TimeInterval(tRL + tAC, tRL + tAC + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL,
sc_time_stamp() + tWL + burstDuration);
return TimeInterval(tWL, tWL + burstDuration);
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -120,11 +120,9 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tDQSCK,
sc_time_stamp() + tRL + tDQSCK + burstDuration);
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tDQSS,
sc_time_stamp() + tWL + tDQSS + burstDuration);
return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration);
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");

8
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -72,6 +72,7 @@ Controller::Controller(sc_module_name name) :
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
ranksNumberOfPayloads = std::vector<unsigned>(memSpec->numberOfRanks);
phyDelay = config.phyDelay;
// reserve buffer for command tuples
readyCommands.reserve(memSpec->numberOfBanks);
@@ -297,7 +298,8 @@ void Controller::controllerMethod()
if (isCasCommand(command))
{
scheduler->removeRequest(payload);
respQueue->insertPayload(payload, memSpec->getIntervalOnDataStrobe(command).end);
respQueue->insertPayload(payload, sc_time_stamp() + phyDelay
+ memSpec->getIntervalOnDataStrobe(command).end);
sc_time triggerTime = respQueue->getTriggerTime();
if (triggerTime != sc_max_time())
@@ -457,8 +459,6 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)
void Controller::sendToDram(Command command, tlm_generic_payload *payload)
{
sc_time delay = SC_ZERO_TIME;
tlm_phase phase = commandToPhase(command);
iSocket->nb_transport_fw(*payload, phase, delay);
iSocket->nb_transport_fw(*payload, phase, phyDelay);
}

2
DRAMSys/library/src/controller/Controller.h
View File

@@ -77,6 +77,8 @@ protected:
SchedulerIF *scheduler;
MemSpec *memSpec;
sc_time phyDelay;
private:
unsigned totalNumberOfPayloads = 0;
std::vector<unsigned> ranksNumberOfPayloads;

6
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -77,12 +77,12 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl
if (isCasCommand(command))
{
TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command);
tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload);
tlmRecorder->updateDataStrobe(sc_time_stamp() + phyDelay + dataStrobe.start,
sc_time_stamp() + phyDelay + dataStrobe.end, *payload);
}
sc_time delay = SC_ZERO_TIME;
tlm_phase phase = commandToPhase(command);
iSocket->nb_transport_fw(*payload, phase, delay);
iSocket->nb_transport_fw(*payload, phase, phyDelay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)

10
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -84,16 +84,16 @@ DRAMSys::DRAMSys(sc_module_name name,
Configuration::getInstance().setPathToResources(pathToResources);
// Load config and initialize modules
Configuration::getInstance().loadMCConfig(Configuration::getInstance(),
pathToResources
+ "configs/mcconfigs/"
+ std::string(simulationdoc["simulation"]["mcconfig"]));
Configuration::getInstance().loadMemSpec(Configuration::getInstance(),
pathToResources
+ "configs/memspecs/"
+ std::string(simulationdoc["simulation"]["memspec"]));
Configuration::getInstance().loadMCConfig(Configuration::getInstance(),
pathToResources
+ "configs/mcconfigs/"
+ std::string(simulationdoc["simulation"]["mcconfig"]));
Configuration::getInstance().loadSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/simulator/"

6
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -133,14 +133,14 @@ void Dram::reportPower()
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &)
tlm_phase &phase, sc_time &delay)
{
assert(phase >= 5 && phase <= 21);
if (Configuration::getInstance().powerAnalysis)
{
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
unsigned long long cycle = sc_time_stamp() / memSpec->tCK;
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}

4
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -117,13 +117,13 @@ void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase
template<class BaseDram>
void DramRecordable<BaseDram>::powerWindow()
{
unsigned long long clkCycles = 0;
int64_t clkCycles = 0;
do {
// At the very beginning (zero clock cycles) the energy is 0, so we wait first
wait(powerWindowSize);
clkCycles = sc_time_stamp() / this->memSpec->tCK;
clkCycles = static_cast<int64_t>(sc_time_stamp() / this->memSpec->tCK + 0.5);
this->DRAMPower->calcWindowEnergy(clkCycles);

7
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -177,14 +177,14 @@ DramWideIO::~DramWideIO()
}
tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &)
tlm_phase &phase, sc_time &delay)
{
assert(phase >= 5 && phase <= 19);
if (Configuration::getInstance().powerAnalysis)
{
unsigned bank = DramExtension::getExtension(payload).getBank().ID();
unsigned long long cycle = sc_time_stamp() / memSpec->tCK;
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}
@@ -203,6 +203,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
}
else if (storeMode == Configuration::StoreMode::ErrorModel)
{
// TODO: delay should be considered here!
unsigned bank = DramExtension::getExtension(payload).getBank().ID();
if (phase == BEGIN_ACT)