From fbf117d0a954b8e20da9c4bfe0032cb67f4298c6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 13 Jan 2021 11:33:21 +0100 Subject: [PATCH] Include PHY delay. --- DRAMSys/library/src/configuration/Configuration.cpp | 6 ++++++ DRAMSys/library/src/configuration/Configuration.h | 4 +++- .../library/src/configuration/memspec/MemSpecDDR3.cpp | 4 ++-- .../library/src/configuration/memspec/MemSpecDDR4.cpp | 4 ++-- .../library/src/configuration/memspec/MemSpecDDR5.cpp | 4 ++-- .../library/src/configuration/memspec/MemSpecGDDR5.cpp | 8 ++++---- .../src/configuration/memspec/MemSpecGDDR5X.cpp | 8 ++++---- .../library/src/configuration/memspec/MemSpecGDDR6.cpp | 8 ++++---- .../library/src/configuration/memspec/MemSpecHBM2.cpp | 6 ++---- .../src/configuration/memspec/MemSpecLPDDR4.cpp | 8 ++++---- .../src/configuration/memspec/MemSpecWideIO.cpp | 6 ++---- .../src/configuration/memspec/MemSpecWideIO2.cpp | 6 ++---- DRAMSys/library/src/controller/Controller.cpp | 8 ++++---- DRAMSys/library/src/controller/Controller.h | 2 ++ .../library/src/controller/ControllerRecordable.cpp | 6 +++--- DRAMSys/library/src/simulation/DRAMSys.cpp | 10 +++++----- DRAMSys/library/src/simulation/dram/Dram.cpp | 6 +++--- DRAMSys/library/src/simulation/dram/DramRecordable.cpp | 4 ++-- DRAMSys/library/src/simulation/dram/DramWideIO.cpp | 7 ++++--- 19 files changed, 60 insertions(+), 55 deletions(-) diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 04c03378..7f4f3394 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -181,6 +181,12 @@ void Configuration::setParameter(std::string name, nlohmann::json value) powerDownTimeout = value; else if (name == "MaxActiveTransactions") maxActiveTransactions = value; + else if (name == "ArbitrationDelay") + arbitrationDelay = memSpec->tCK * value; + else if (name == "ThinkDelay") + thinkDelay = memSpec->tCK * value; + else if (name == "PhyDelay") + phyDelay = memSpec->tCK * value; //SimConfig------------------------------------------------ else if (name == "SimulationName") simulationName = value; diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index 71c578f0..a236275e 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -82,6 +82,9 @@ public: enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy; unsigned int powerDownTimeout = 3; unsigned int maxActiveTransactions = 64; + sc_time arbitrationDelay = SC_ZERO_TIME; + sc_time thinkDelay = SC_ZERO_TIME; + sc_time phyDelay = SC_ZERO_TIME; // SimConfig std::string simulationName = "default"; @@ -95,7 +98,6 @@ public: bool checkTLM2Protocol = false; enum class ECCMode {Disabled, Hamming} eccMode; ECCBaseClass *pECC = nullptr; - bool gem5 = false; bool useMalloc = false; unsigned long long int addressOffset = 0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 7cc92848..2da79c88 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -123,9 +123,9 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration); + return TimeInterval(tRL, tRL + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration); + return TimeInterval(tWL, tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 23f6773e..cd6daac4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -142,9 +142,9 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration); + return TimeInterval(tRL, tRL + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration); + return TimeInterval(tWL, tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index bd5e92ef..5d0353c8 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -185,9 +185,9 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + cmdOffset_L, sc_time_stamp() + tRL + burstDuration + cmdOffset_L); + return TimeInterval(tRL + cmdOffset_L, tRL + burstDuration + cmdOffset_L); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + cmdOffset_L, sc_time_stamp() + tWL + burstDuration + cmdOffset_L); + return TimeInterval(tWL + cmdOffset_L, tWL + burstDuration + cmdOffset_L); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index f99ce411..2c27dbc3 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -131,11 +131,11 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index 84f581fa..ea1dc46e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -131,11 +131,11 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 4cde4e10..d296f887 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -133,11 +133,11 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); else { SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 3f61973b..ea91854b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -128,11 +128,9 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + burstDuration); + return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + burstDuration); + return TimeInterval(tWL, tWL + burstDuration); else { SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index ca0a2fc1..29e5fb5c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -135,11 +135,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * tCK, - sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * tCK); + return TimeInterval(tRL + tDQSCK + 3 * tCK, + tRL + tDQSCK + burstDuration + 3 * tCK); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * tCK, - sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK); + return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK, + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK); else { SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index f0df06df..36ff96ea 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -129,11 +129,9 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tAC, - sc_time_stamp() + tRL + tAC + burstDuration); + return TimeInterval(tRL + tAC, tRL + tAC + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + burstDuration); + return TimeInterval(tWL, tWL + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 97006423..1678d2d5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -120,11 +120,9 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + burstDuration); + return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tDQSS, - sc_time_stamp() + tWL + tDQSS + burstDuration); + return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 7e870207..5f0be9ef 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -72,6 +72,7 @@ Controller::Controller(sc_module_name name) : Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; ranksNumberOfPayloads = std::vector(memSpec->numberOfRanks); + phyDelay = config.phyDelay; // reserve buffer for command tuples readyCommands.reserve(memSpec->numberOfBanks); @@ -297,7 +298,8 @@ void Controller::controllerMethod() if (isCasCommand(command)) { scheduler->removeRequest(payload); - respQueue->insertPayload(payload, memSpec->getIntervalOnDataStrobe(command).end); + respQueue->insertPayload(payload, sc_time_stamp() + phyDelay + + memSpec->getIntervalOnDataStrobe(command).end); sc_time triggerTime = respQueue->getTriggerTime(); if (triggerTime != sc_max_time()) @@ -457,8 +459,6 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { - sc_time delay = SC_ZERO_TIME; tlm_phase phase = commandToPhase(command); - - iSocket->nb_transport_fw(*payload, phase, delay); + iSocket->nb_transport_fw(*payload, phase, phyDelay); } diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 20e6b3ad..e1798a56 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -77,6 +77,8 @@ protected: SchedulerIF *scheduler; MemSpec *memSpec; + sc_time phyDelay; + private: unsigned totalNumberOfPayloads = 0; std::vector ranksNumberOfPayloads; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index c8ab5efd..efee8326 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -77,12 +77,12 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl if (isCasCommand(command)) { TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); - tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); + tlmRecorder->updateDataStrobe(sc_time_stamp() + phyDelay + dataStrobe.start, + sc_time_stamp() + phyDelay + dataStrobe.end, *payload); } - sc_time delay = SC_ZERO_TIME; tlm_phase phase = commandToPhase(command); - iSocket->nb_transport_fw(*payload, phase, delay); + iSocket->nb_transport_fw(*payload, phase, phyDelay); } void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index c0d2c123..1e76d1d9 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -84,16 +84,16 @@ DRAMSys::DRAMSys(sc_module_name name, Configuration::getInstance().setPathToResources(pathToResources); // Load config and initialize modules - Configuration::getInstance().loadMCConfig(Configuration::getInstance(), - pathToResources - + "configs/mcconfigs/" - + std::string(simulationdoc["simulation"]["mcconfig"])); - Configuration::getInstance().loadMemSpec(Configuration::getInstance(), pathToResources + "configs/memspecs/" + std::string(simulationdoc["simulation"]["memspec"])); + Configuration::getInstance().loadMCConfig(Configuration::getInstance(), + pathToResources + + "configs/mcconfigs/" + + std::string(simulationdoc["simulation"]["mcconfig"])); + Configuration::getInstance().loadSimConfig(Configuration::getInstance(), pathToResources + "configs/simulator/" diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index b19d34b1..6622b557 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -133,14 +133,14 @@ void Dram::reportPower() } tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &) + tlm_phase &phase, sc_time &delay) { assert(phase >= 5 && phase <= 21); if (Configuration::getInstance().powerAnalysis) { - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); - unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int64_t cycle = static_cast((sc_time_stamp() + delay) / memSpec->tCK + 0.5); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index c8dd5b6a..4c6701ce 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -117,13 +117,13 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase template void DramRecordable::powerWindow() { - unsigned long long clkCycles = 0; + int64_t clkCycles = 0; do { // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = sc_time_stamp() / this->memSpec->tCK; + clkCycles = static_cast(sc_time_stamp() / this->memSpec->tCK + 0.5); this->DRAMPower->calcWindowEnergy(clkCycles); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 1f9b7a79..4e37cd09 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -177,14 +177,14 @@ DramWideIO::~DramWideIO() } tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &) + tlm_phase &phase, sc_time &delay) { assert(phase >= 5 && phase <= 19); if (Configuration::getInstance().powerAnalysis) { - unsigned bank = DramExtension::getExtension(payload).getBank().ID(); - unsigned long long cycle = sc_time_stamp() / memSpec->tCK; + int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); + int64_t cycle = static_cast((sc_time_stamp() + delay) / memSpec->tCK + 0.5); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } @@ -203,6 +203,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, } else if (storeMode == Configuration::StoreMode::ErrorModel) { + // TODO: delay should be considered here! unsigned bank = DramExtension::getExtension(payload).getBank().ID(); if (phase == BEGIN_ACT)