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Author SHA1 Message Date
Lukas Steiner
e0743b71d6 Small improvement in ControllerNew (redundant event triggers), renaming in ControllerState. 2019-07-28 20:45:03 +02:00
Lukas Steiner
733525e787 Included command mux which selects the oldest payload and a command mux interface. 2019-07-27 21:12:22 +02:00
Lukas Steiner
215790a931 Created different schedulers (Fifo and FrFcfs) and a scheduler interface. 2019-07-27 19:24:09 +02:00
Lukas Steiner (2)
c4c2640594 Moved event trigger out of BankMachine. 2019-07-26 16:28:22 +02:00
Lukas Steiner (2)
3f913b5c16 Arbiter now assigns each payload an ID for transaction order decision in CommandMux. 2019-07-26 15:48:58 +02:00
Lukas Steiner (2)
f2ab2fe3ee Included first test for CommandMux. 2019-07-25 16:40:03 +02:00
Lukas Steiner (2)
38a21088a0 Merge branch 'master' into DRAMSys4.0_ctrl 2019-07-25 13:47:57 +02:00
Matthias Jung
7304055a22 Merge branch 'googletest_merge2' into 'master' 
Include googletest and subproject for unit tests.

See merge request ems/astdm/dram.sys!240
 2019-07-25 12:02:33 +02:00
Lukas Steiner (2)
a303f242e6 Included googletest and subproject for unit tests. 2019-07-25 11:49:18 +02:00
Lukas Steiner
7bd0950e1e Some minor changes. 2019-07-23 21:30:29 +02:00
Lukas Steiner (2)
e1e53b5c2e Moved parts of logic from CommandMux::selectCommand to controlMethod, moved commandFinishedTime from BMs to Controller. 2019-07-23 16:20:38 +02:00
Lukas Steiner (2)
1e8b8e37ea Moved if statements from inner methods to controllerMethod(). 2019-07-23 15:10:19 +02:00
Lukas Steiner (2)
e7552f6916 Code cleanup. 2019-07-23 14:30:01 +02:00
Lukas Steiner (2)
0d0c7415b2 Fixed clk cycle waiting for fifo strict transaction order. 2019-07-23 14:13:51 +02:00
Lukas Steiner
6aa2533edd New controller is working. 2019-07-22 20:31:17 +02:00
Lukas Steiner
f69771e7be Simulation is running to the end, results may still be wrong. 2019-07-22 17:59:51 +02:00
Lukas Steiner
1ce8996ece Some bugs are fixed, still not running. 2019-07-22 01:53:18 +02:00
Lukas Steiner
ef011ad52c Ready for debugging. 2019-07-22 00:23:12 +02:00
Lukas Steiner
9204a88a28 Included some functionality, included scheduler. 2019-07-20 23:32:37 +02:00
Lukas Steiner (2)
cd5b5cb423 Included new controller classes. 2019-07-20 15:53:30 +02:00
Lukas Steiner (2)
41e2db0b5a Removed refresh and power down. 2019-07-19 10:29:14 +02:00
Lukas Steiner (2)
f43ea71e95 Minor changes in new timing checker. 2019-07-16 15:52:02 +02:00
Lukas Steiner (2)
be83ad01cb Included remaining commands. 2019-07-11 15:22:09 +02:00
Lukas Steiner (2)
9be64edaa9 Added commands ACT, PRE, PREA, RD, RDA, WR, WRA, PDEA, PDEP to new timing checker. 2019-07-10 15:55:45 +02:00
Lukas Steiner (2)
3e4e8e9408 Included new timing checker for DDR3. 2019-07-09 15:52:09 +02:00
Lukas Steiner (2)
cb393b8abf Renaming of commands, TODOs in timing checkers. 2019-07-05 16:17:52 +02:00
Lukas Steiner (2)
37b2dc9e4d Renaming of commands according to DRAMml. 2019-07-04 10:13:19 +02:00
Lukas Steiner (2)
34626448bb RefMode (tRFC) is now only configurable during initialization. 2019-07-02 16:25:43 +02:00
Lukas Steiner (2)
41cc447d86 Included timing parameters for RGR. 2019-07-02 14:25:53 +02:00
Lukas Steiner (2)
ffdc67945a Removed specific DRAMPower configuration in DRAMs. 2019-07-01 15:00:01 +02:00
Lukas Steiner (2)
50f90176a0 Included specific timing parameters for different DRAMs. 2019-07-01 11:16:36 +02:00
Lukas Steiner (2)
3b509a7c17 Marked old timing parameters with "_old" for inclusion of new ones without conflicts. 2019-07-01 10:23:30 +02:00
Lukas Steiner
9b8729c58b Bugfix: nbrOfRanks is only part of some memspecs for WideIO. 2019-06-28 17:53:52 +02:00
Lukas Steiner
409e49f044 Bugfix: call loadCommons() only after creating a memSpec object. 2019-06-28 17:36:51 +02:00
Lukas Steiner (2)
21adf2ac70 Moved some timings to loadCommons(). 2019-06-28 16:26:46 +02:00
Lukas Steiner (2)
a5fb1327a1 Renaming of timings. 2019-06-28 15:14:47 +02:00
Lukas Steiner (2)
7da2aacfa3 Separate constructors for each DRAM type. 2019-06-28 14:40:07 +02:00
Lukas Steiner (2)
72152bca8b Included GenericController for later verilator inclusion. 2019-06-28 14:10:09 +02:00
Lukas Steiner (2)
ac4e4c7783 Moved specific timing calculation functions to MemSpecs. 2019-06-27 16:02:24 +02:00
Lukas Steiner
e462287d7c Split up timings. 2019-06-25 22:40:18 +02:00
Lukas Steiner
2d08d48f81 Bugfix: Wrong header included. Removed redundant main function. 2019-06-25 19:49:03 +02:00
Lukas Steiner (2)
51e6ebfed0 CheckerDDR3 works, timings may still be wrong. 2019-06-25 15:56:22 +02:00
Lukas Steiner (2)
c0d6231e26 Adapted timings for CheckerDDR3. 2019-06-25 14:24:39 +02:00
Lukas Steiner (2)
4c4119803e Included CheckerDDR3. 2019-06-25 13:37:49 +02:00
Matthias Jung
70b9ec8517 Merge branch 'DRAMSys4.0_dev' into 'master' 
Specific DRAMs and MemSpecs, renamed schedulers.

See merge request ems/astdm/dram.sys!236
 2019-06-24 16:10:33 +02:00
Lukas Steiner (2)
188c552d5f Merge remote-tracking branch 'origin/DRAMSys4.0_merge' into DRAMSys4.0_dev 
# Conflicts:
#	DRAMSys/library/library.pro
#	DRAMSys/library/src/simulation/DRAMSys.cpp
#	DRAMSys/library/src/simulation/DramDDR3.cpp
#	DRAMSys/library/src/simulation/DramDDR3.h
#	DRAMSys/library/src/simulation/DramDDR4.cpp
#	DRAMSys/library/src/simulation/DramDDR4.h
#	DRAMSys/library/src/simulation/DramRecordable.cpp
#	DRAMSys/library/src/simulation/DramRecordable.h
#	DRAMSys/library/src/simulation/DramWideIO.h
 2019-06-24 14:13:05 +02:00
Lukas Steiner (2)
d07a775697 Annotations for different MemSpecs. 2019-06-24 13:59:57 +02:00
Lukas Steiner (2)
45b05c5cf0 Created DramWideIO, removed powerAnalysis switch. 2019-06-24 11:59:59 +02:00
Lukas Steiner
21c243b9d3 Replaced "BaseDram::" with "this->" to access members of the base class. 2019-06-23 21:20:21 +02:00
Lukas Steiner
f8baef57c6 Adapting current DRAM to new structure. 2019-06-23 20:53:08 +02:00