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Author SHA1 Message Date
Lukas Steiner (2)
bda10dca2f Individual memspec files for different DRAMs. 2019-09-23 14:31:47 +02:00
Lukas Steiner (2)
c1b741d89b Changed directory of configuration, added attribute unused to suppress warnings. 2019-09-23 13:24:47 +02:00
Lukas Steiner (2)
650e1d405b Removed ScheduledCommand dependencies. 2019-09-23 10:23:02 +02:00
Lukas Steiner
5fe5529c7c Included various command lengths. 2019-09-20 17:35:01 +02:00
Lukas Steiner
97542d5f97 Included missing memory allocation in Dram. 2019-09-19 14:46:55 +02:00
Lukas Steiner
d06d9eec2c Changed data structures of timing checkers from ScheduledCommand to sc_time. 2019-09-19 14:45:38 +02:00
Lukas Steiner
b918f0f9ea Added ranks to tdb files and TraceAnalyzer. 2019-09-18 18:24:10 +02:00
Lukas Steiner
330b07d0e7 Changed data structures of Address Decoder for speedup. 2019-09-18 16:39:38 +02:00
Lukas Steiner
6eef8ff1e6 Rank inclusion part 2. 2019-09-17 21:31:57 +02:00
Lukas Steiner
5d7495383e Changed internal data structures from std::map to std::vector for faster access. 2019-09-17 18:16:52 +02:00
Lukas Steiner (2)
3a7557544f Rank inclusion part 1. 2019-09-16 15:16:14 +02:00
Lukas Steiner (2)
b9700f1ee5 Implemented some basics for ranks. 2019-09-12 14:56:06 +02:00
Lukas Steiner (2)
26c3bd23c1 Changed default colour grouping to phase. 2019-09-12 10:55:59 +02:00
Lukas Steiner
fcde31f041 Included adaptive page policy. 2019-09-11 20:36:45 +02:00
Lukas Steiner (2)
62841a3590 Implemented closed page policy. Fixed bug in trace analyzer tests. 2019-09-11 16:02:36 +02:00
Lukas Steiner (2)
7fd5f05d3e Renaming of ControllerNew to Controller. 2019-09-11 09:59:51 +02:00
Lukas Steiner (2)
7827a5f869 Added some addressmappings and memspecs for WIDEIO and WIDEIO2. 2019-09-10 15:22:05 +02:00
Lukas Steiner (2)
f40ace826b Changed DRAMPower submodule commit and branch. 2019-08-26 17:14:23 +02:00
Lukas Steiner (2)
7934d2e160 Renaming libDRAMPowerIF to libDRAMPowerDummy. 2019-08-26 16:26:28 +02:00
Lukas Steiner
2402180a9c Merge branch 'DRAMSys4.0_ctrl' of https://git.eit.uni-kl.de/ems/astdm/dram.sys into DRAMSys4.0_ctrl 2019-08-25 23:14:19 +02:00
Lukas Steiner
d4943bccc5 Debug Manager cleanup. 2019-08-25 23:13:05 +02:00
Lukas Steiner (2)
98c52b8a3e Merge remote-tracking branch 'origin/master' into DRAMSys4.0_ctrl 
# Conflicts:
#	DRAMSys/library/src/simulation/MemoryManager.cpp
 2019-08-23 09:54:56 +02:00
Matthias Jung
f6072e9d4f Fixed Memory Leak 
As pointed out by @sprado, there was a memory leak in the STL player.
The data pointer was allocated, but never deleted again. Some lines for
deletion were commented out in the memory manager in the free function.
These two lines regarding the deletion of data were moved into the
destructor of the memory manager. The allocation of the data is done in
the allocate() function of the memory manager when a new payload is
generated.
 2019-08-22 23:11:48 +02:00
Matthias Jung
d55d801a04 Merge branch 'master' of https://git.eit.uni-kl.de/ems/astdm/dram.sys 2019-08-22 23:03:05 +02:00
Matthias Jung
a6f679b86b Add compile flag for macOS 2019-08-22 23:00:38 +02:00
Matthias Jung
9702d7a8f3 Add compile flag for macOS 2019-08-22 22:59:23 +02:00
Matthias Jung
6388b3d75c DRAM command was not set in trace recorder 2019-08-22 22:40:28 +02:00
Lukas Steiner
f5f3c729e0 Temporary fix of memory leak. 2019-08-22 22:16:33 +02:00
Lukas Steiner (2)
1fc5f3bf88 Some phase renaming in TraceAnalyzer. 2019-08-20 14:56:45 +02:00
Lukas Steiner (2)
4881b8ae76 Implemented initial version of timing checker for WideIO. 2019-08-20 10:58:28 +02:00
Lukas Steiner (2)
2ef1c2b189 Removed RefreshCheckerIF, RefreshCheckerDummy is now used as base class. 2019-08-20 10:11:56 +02:00
Lukas Steiner (2)
baa976dac4 Removed unused commands and extended protocol phases. 2019-08-20 09:51:55 +02:00
Lukas Steiner (2)
cbeaef32de Removed specific memspec dependency in RefreshManager, changed RefreshChecker to RefreshCheckerDDR3. 2019-08-19 16:17:31 +02:00
Lukas Steiner (2)
7c87b954ec Removed different refresh timings for different banks, removed ORGR parameters from mcconfigs. 2019-08-19 15:11:49 +02:00
Lukas Steiner (2)
35af025d4c Removed unused configuration parameters, moved some currents and voltages to specific memspecs. 2019-08-19 13:51:27 +02:00
Lukas Steiner (2)
3f7296f2a5 Removed RGR timing parameters. 2019-08-19 11:16:27 +02:00
Lukas Steiner
8115aba222 Fixed wrong PRE -<> PREA test in TraceAnalyzer. 2019-08-18 19:56:17 +02:00
Lukas Steiner
4d936892d9 Included DRAMPower dummy, it can now be switched on and off again. 2019-08-18 19:23:53 +02:00
Lukas Steiner (2)
7b8bb86620 Removed old timing parameters, moved DramPower configuration to specific Drams. 2019-08-15 14:55:55 +02:00
Lukas Steiner
7d675a9837 Renaming and minor improvements. 2019-08-14 21:19:42 +02:00
Lukas Steiner
31101a0827 Finished bankwise refresh. 2019-08-14 20:19:27 +02:00
Lukas Steiner (2)
47ee187bc3 Working on RefreshManagerBankwise. 2019-08-14 13:48:04 +02:00
Lukas Steiner (2)
0918a78648 Included GenericController for polymorphism. 2019-08-14 09:44:24 +02:00
Lukas Steiner (2)
c2022667c5 Included files for RefreshManagerBankwise. 2019-08-13 14:23:44 +02:00
Lukas Steiner (2)
3b26997ea4 Updated structure of RefreshManager for bankwise refresh implementation. 2019-08-13 11:39:15 +02:00
Lukas Steiner (2)
38a099b8e8 Included RefreshChecker for different refresh modes. 2019-08-12 16:41:44 +02:00
Lukas Steiner (2)
e6dc4e7c75 Removed unused files of old controller. 2019-08-12 14:19:22 +02:00
Lukas Steiner
05a8272ee6 Moved bandwidth calculation to GenericController. 2019-08-10 01:01:52 +02:00
Lukas Steiner
dc194781f7 Code formatting. 2019-08-09 23:46:49 +02:00
Lukas Steiner
08dc5e811a Removed redundant check in controllerMethod. 2019-08-09 23:45:17 +02:00