7a32613cb3
Switch to <filesystem> remove operation
2024-09-25 11:00:09 +02:00
2465f06d14
Minor fixes in the Trace Analyzer
2024-07-18 10:16:36 +02:00
82027bfa83
Move Trace Analyzer to open source tree
...
Move the code for the Trace Analyzer to the open source tree and only
keep the extensions behind a compiler flag.
2024-07-18 10:13:25 +02:00
Lukas Steiner
3d9d12ea65
Merge branch 'buffer_warning' into 'develop'
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Add a warning when RequestBufferSize is configured together with ReadWrite SchedulerBuffer
See merge request ems/astdm/modeling.dram/dram.sys.5!67
2024-07-18 07:49:40 +00:00
5dd7c22a74
Refactor CMakeLists and GitLab CI/CD pipeline
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- Remove nested minimum required to supress warnings.
- Declare SystemC as system library to supress warnings in headers.
- Add a BUILD_SHARED_LIBS option
- Remove hardcoded STATIC in various add_library calls to honor the
BUILD_SHARED_LIBS option
- Remove _deps/ directory from the build directory in GitLab pipeline
- Remove *.tdb files after test stage in pipeline
- Set Ninja as the default generator for the dev preset and re-enable
colored diagnostics
2024-06-28 11:07:56 +02:00
7274770a0f
Add a warning when RequestBufferSize is configured together with ReadWrite SchedulerBuffer
2024-05-08 10:09:20 +02:00
Lukas Steiner
5b4ed9559d
Merge branch 'config_refactor' into 'develop'
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Configuration Refactoring
See merge request ems/astdm/modeling.dram/dram.sys.5!63
2024-02-23 14:29:06 +00:00
0ec6ea79ad
Migrate from clkMhz to tCK entry in memspecs
2024-02-23 12:04:22 +01:00
1a2e5497ee
Fix AddressDecoderTest
2024-02-23 11:59:50 +01:00
3925c5be55
Remove unused ReorderBuffer
2024-02-23 11:54:51 +01:00
59cf73fe9c
Clean up public API (DRAMSys.h)
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Remove DRAMSysRecordable.h/cpp as the functionality has been incorporated into
DRAMSys.h/cpp. The databaseRecording config is now completely handled by
DRAMSys itself without needing the user of the library to instanciate DRAMSys
or DRAMSysRecordable depending on this config.
2024-02-23 11:54:51 +01:00
5391b4351d
Fix configuration tests
2024-02-23 11:54:51 +01:00
454cb00ddb
Refactor: remove monolithic configuration class
2024-02-23 11:54:51 +01:00
d92ea325c3
Remove ControllerIF.h
...
It provided no advantage and made things unecessary complicated
2024-02-23 11:49:08 +01:00
Lukas Steiner
5eabecc9f9
Merge branch 'odr_fix' into 'develop'
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Fix ODR violation of Dram and DramRecordable
See merge request ems/astdm/modeling.dram/dram.sys.5!64
2024-02-23 09:05:50 +00:00
Lukas Steiner
c7a4e31f2f
Merge branch 'work/addressdecoder' into 'develop'
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Add support for arbitrary XOR address manipulation
See merge request ems/astdm/modeling.dram/dram.sys.5!60
2024-02-23 08:33:59 +00:00
60d3e7618b
Fix ODR violation of Dram and DramRecordable
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The compiler flag DRAMPower was not propagated to downstream projects,
leading to an ODR violation of the classes Dram and DramRecordable
2024-02-08 11:47:34 +01:00
7b743db820
Add simple benchmark of full DDR3 simulation
2023-12-14 10:04:45 +01:00
1ba63bd1f7
Add support for more than two XOR bits
2023-12-13 10:32:03 +01:00
a89f4a3065
Introduce benchmark support using Google Benchmark
2023-12-11 11:33:11 +01:00
ed2a675145
Extract plausability check from AddressDecoder to separate function
2023-12-11 10:32:39 +01:00
6e0110190e
Introduce executeRead() and executeWrite() functions
2023-11-20 16:22:02 +01:00
Lukas Steiner
0b88161640
Merge branch 'DramCleanup' into 'develop'
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Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files
See merge request ems/astdm/modeling.dram/dram.sys.5!58
2023-11-16 13:25:16 +00:00
6645a9ed54
Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files
2023-11-14 14:57:25 +01:00
74a9155993
Add RequestBufferSizeRead and RequestBufferSizeWrite configurations for ReadWrite Buffer
2023-11-14 11:00:28 +01:00
d2e5bd36de
Fix all warnings
2023-09-22 10:45:23 +02:00
Lukas Steiner
8224e97abe
Reformat all files.
2023-09-21 16:50:59 +02:00
Lukas Steiner
68d82cd209
Merge branch 'work/serde' into 'develop'
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Introduce Serialize/Deserialize interfaces
See merge request ems/astdm/modeling.dram/dram.sys.5!44
2023-09-19 12:44:45 +00:00
Lukas Steiner
9e53a38132
Fix address mapping for single device without byte bits.
2023-08-31 13:43:49 +02:00
a5810e48f4
Fix recording of memspec and mcconfig in trace database
2023-08-31 11:25:26 +02:00
41343c787e
Introduce a concept to report idling to the outside
2023-08-31 10:19:04 +02:00
f96bdd4ac1
Introduce a serialize/deserialize interface
2023-08-31 10:19:01 +02:00
692ac5e566
Fix StlPlayer to store real data
2023-08-31 09:34:35 +02:00
c07d09f392
Format all files
2023-08-29 09:26:25 +02:00
1bb3c3ea0f
Use raw string literal for database creation
2023-08-29 09:22:45 +02:00
Lukas Steiner
ccb4ee592b
Remove masked write from GDDR checkers.
2023-08-23 15:30:15 +02:00
Lukas Steiner
12f2b73cde
Additional check of byte enable pointer.
2023-08-23 15:21:53 +02:00
Lukas Steiner
0f824e8b92
Do not allow masked write in default case.
2023-08-23 11:41:58 +02:00
a539e3c011
Merge branch 'develop' into work/partial_writes
2023-08-23 09:31:42 +02:00
0d67a1fc2b
Support byte_enable_ptr for debug transport
2023-08-22 11:26:28 +02:00
47bdddc5f1
Different tCCDMW timing when previous WR had BL32 in LPDDR4
2023-08-22 09:41:36 +02:00
4548d20b6e
Rename requiresMaskedWrite to requiresReadModifyWrite
2023-08-21 10:55:41 +02:00
f1cfb80337
Minor readability fixes
2023-08-21 10:10:49 +02:00
a0f93a75e2
Merge develop
2023-08-21 10:01:08 +02:00
b30df49d67
Use tCCDMW for masked write in LPDDR4
2023-08-21 09:26:05 +02:00
3f0372f1f7
Add Partial Write support for blocking accesses
2023-08-16 09:45:32 +02:00
570fb985df
Fix MWR and MWRA command lengths for LPDDR4
2023-08-16 09:38:57 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
40dbc518b6
Add hack in TimingCheckers to convert MWR to WR in insertion stage
2023-08-16 09:38:54 +02:00
f7066a22b0
First implementation of Partial Writes
2023-08-16 09:38:54 +02:00
