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Implement Partial Write for DDR5

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This commit is contained in:
Derek Christ
2023-08-15 11:57:28 +02:00
parent 40dbc518b6
commit c5f1320399
11 changed files with 27 additions and 25 deletions
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2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -148,7 +148,7 @@ bool MemSpec::hasRasAndCasBus() const
return false;
}
bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{
return payload.get_byte_enable_ptr() != nullptr;
}

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -102,7 +102,7 @@ public:
virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const;
sc_core::sc_time getCommandLength(Command) const;
double getCommandLengthInCycles(Command) const;

16
src/libdramsys/DRAMSys/controller/BankMachine.cpp
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@@ -70,11 +70,11 @@ void BankMachine::update(Command command)
state = State::Precharged;
keepTrans = false;
break;
case Command::RD: case Command::WR:
case Command::RD: case Command::WR: case Command::MWR:
currentPayload = nullptr;
keepTrans = false;
break;
case Command::RDA: case Command::WRA:
case Command::RDA: case Command::WRA: case Command::MWRA:
state = State::Precharged;
currentPayload = nullptr;
keepTrans = false;
@@ -201,7 +201,7 @@ void BankMachineOpen::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else // row miss
@@ -247,7 +247,7 @@ void BankMachineClosed::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}
@@ -295,7 +295,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
else
@@ -305,7 +305,7 @@ void BankMachineOpenAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
}
@@ -357,7 +357,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RD;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
}
}
else
@@ -367,7 +367,7 @@ void BankMachineClosedAdaptive::evaluate()
nextCommand = Command::RDA;
else
{
nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
}
}
}

2
src/libdramsys/DRAMSys/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -181,7 +181,7 @@ void RefreshManagerAllBank::update(Command command)
case Command::ACT:
activatedBanks++;
break;
case Command::PREPB: case Command::RDA: case Command::WRA:
case Command::PREPB: case Command::RDA: case Command::WRA: case Command::MWRA:
activatedBanks--;
break;
case Command::PREAB: