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Migrate from clkMhz to tCK entry in memspecs

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This commit is contained in:
Derek Christ
2023-12-18 10:50:32 +01:00
parent 5eabecc9f9
commit 0ec6ea79ad
178 changed files with 188 additions and 194 deletions
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3
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -75,8 +75,7 @@ MemSpec::MemSpec(const DRAMSys::Config::MemSpec& memSpec,
bytesPerBeat(dataBusWidth / 8),
defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
fCKMHz(memSpec.memtimingspec.entries.at("clkMhz")),
tCK(sc_time(1.0 / fCKMHz, SC_US)),
tCK(sc_time(memSpec.memtimingspec.entries.at("tCK"), SC_PS)),
memoryId(memSpec.memoryId),
memoryType(memoryType),
burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate))

1
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -83,7 +83,6 @@ public:
const unsigned maxBytesPerBurst;
// Clock
const double fCKMHz;
const sc_core::sc_time tCK;
const std::string memoryId;

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
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@@ -211,9 +211,9 @@ DRAMPower::MemorySpecification MemSpecDDR3::toDramPowerMemSpec() const
memTimingSpec.CCD_S = tCCD / tCK;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tFAW / tCK;
memTimingSpec.RAS = tRAS / tCK;

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
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@@ -231,9 +231,9 @@ DRAMPower::MemorySpecification MemSpecDDR4::toDramPowerMemSpec() const
memTimingSpec.CCD_S = tCCD_S / tCK;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tFAW / tCK;
memTimingSpec.RAS = tRAS / tCK;

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
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@@ -226,9 +226,9 @@ DRAMPower::MemorySpecification MemSpecWideIO::toDramPowerMemSpec() const
memTimingSpec.CCD_S = defaultBurstLength;
memTimingSpec.CKE = tCKE / tCK;
memTimingSpec.CKESR = tCKESR / tCK;
memTimingSpec.clkMhz = fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / fCKMHz;
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
memTimingSpec.DQSCK = tDQSCK / tCK;
memTimingSpec.FAW = tTAW / tCK;
memTimingSpec.RAS = tRAS / tCK;