First implementation of Partial Writes

2023-08-14 10:36:35 +02:00
parent a8d15e35a5
commit f7066a22b0
35 changed files with 271 additions and 194 deletions
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
@@ -148,4 +148,9 @@ bool MemSpec::hasRasAndCasBus() const
    return false;
 }

+bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
@@ -102,6 +102,8 @@ public:
    virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;

+    virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
+
    sc_core::sc_time getCommandLength(Command) const;
    double getCommandLengthInCycles(Command) const;
    uint64_t getSimMemSizeInBytes() const;
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp
@@ -137,9 +137,9 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
        return tRL + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -155,7 +155,7 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm_gen
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL, tRL + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL, tWL + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
@@ -156,9 +156,9 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
        return tRL + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -174,7 +174,7 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tl
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL, tRL + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL, tWL + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp
@@ -141,9 +141,9 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
        return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -161,7 +161,7 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_ge
 {
    if (command == Command::RD || command == Command::RDA)
        return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp
@@ -141,9 +141,9 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
        return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -161,7 +161,7 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_g
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp
@@ -154,9 +154,9 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
        return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFCab;
@@ -174,7 +174,7 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_ge
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp
@@ -142,9 +142,9 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
        return tRL + tDQSCK + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -162,7 +162,7 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_gen
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL, tWL + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
@@ -144,9 +144,9 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
        return tRL + tDQSCK + burstDuration + 3 * tCK;
    else if (command == Command::RDA)
        return burstDuration + tRTP - 5 * tCK + tRPpb;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + 4 * tCK + burstDuration + tWR + tRPpb;
    else if (command == Command::REFAB)
        return tRFCab + tCK;
@@ -164,7 +164,7 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_g
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp
@@ -114,9 +114,9 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl
        return tRL + burstDuration;
    else if (command == Command::RDA)
        return tRTP + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tWR + tRP;
    else
    {
@@ -130,7 +130,7 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm:
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL, tRL + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL, tWL + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp
@@ -143,9 +143,9 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
        return tRL + tAC + burstDuration;
    else if (command == Command::RDA)
        return burstDuration + tRP;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration - tCK + tWR + tRP;
    else if (command == Command::REFAB)
        return tRFC;
@@ -161,7 +161,7 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_g
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tAC, tRL + tAC + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL, tWL + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp
@@ -129,9 +129,9 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
        return tRL + tDQSCK + burstDuration;
    else if (command == Command::RDA)
        return burstDuration - 2 * tCK + tRTP + tRPpb;
-    else if (command == Command::WR)
+    else if (command == Command::WR || command == Command::MWR)
        return tWL + tDQSS + burstDuration;
-    else if (command == Command::WRA)
+    else if (command == Command::WRA || command == Command::MWRA)
        return tWL + burstDuration + tCK + tWR + tRPpb;
    else if (command == Command::REFAB)
        return tRFCab;
@@ -149,7 +149,7 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_
 {
    if (command == Command::RD || command == Command::RDA)
        return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
        return {tWL + tDQSS, tWL + tDQSS + burstDuration};
    else
    {
--- a/src/libdramsys/DRAMSys/controller/BankMachine.cpp
+++ b/src/libdramsys/DRAMSys/controller/BankMachine.cpp
@@ -200,7 +200,9 @@ void BankMachineOpen::evaluate()
                    if (currentPayload->is_read())
                        nextCommand = Command::RD;
                    else
-                        nextCommand = Command::WR;
+                    {
+                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                    }
                }
                else // row miss
                    nextCommand = Command::PREPB;
@@ -244,7 +246,9 @@ void BankMachineClosed::evaluate()
                if (currentPayload->is_read())
                    nextCommand = Command::RDA;
                else
-                    nextCommand = Command::WRA;
+                {
+                    nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                }
            }
        }
    }
@@ -290,7 +294,9 @@ void BankMachineOpenAdaptive::evaluate()
                        if (currentPayload->is_read())
                            nextCommand = Command::RDA;
                        else
-                            nextCommand = Command::WRA;
+                        {
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                        }
                    }
                    else
                    {
@@ -298,7 +304,9 @@ void BankMachineOpenAdaptive::evaluate()
                        if (currentPayload->is_read())
                            nextCommand = Command::RD;
                        else
-                            nextCommand = Command::WR;
+                        {
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                        }
                    }
                }
                else // row miss
@@ -348,7 +356,9 @@ void BankMachineClosedAdaptive::evaluate()
                        if (currentPayload->is_read())
                            nextCommand = Command::RD;
                        else
-                            nextCommand = Command::WR;
+                        {
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                        }
                    }
                    else
                    {
@@ -356,7 +366,9 @@ void BankMachineClosedAdaptive::evaluate()
                        if (currentPayload->is_read())
                            nextCommand = Command::RDA;
                        else
-                            nextCommand = Command::WRA;
+                        {
+                            nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                        }
                    }
                }
                else // row miss, can happen when RD/WR mode is switched
--- a/src/libdramsys/DRAMSys/controller/Command.cpp
+++ b/src/libdramsys/DRAMSys/controller/Command.cpp
@@ -51,7 +51,7 @@ namespace DRAMSys

 bool phaseHasDataStrobe(tlm::tlm_phase phase)
 {
-    return (phase >= BEGIN_RD && phase <= BEGIN_WRA);
+    return (phase >= BEGIN_RD && phase <= BEGIN_MWRA);
 }

 bool isPowerDownEntryPhase(tlm::tlm_phase phase)
@@ -85,26 +85,28 @@ Command::Command(tlm_phase phase)
                    Command::NOP,    // 0
                    Command::RD,     // 1
                    Command::WR,     // 2
-                    Command::RDA,    // 3
-                    Command::WRA,    // 4
-                    Command::ACT,    // 5
-                    Command::PREPB,  // 6
-                    Command::REFPB,  // 7
-                    Command::RFMPB,  // 8
-                    Command::REFP2B, // 9
-                    Command::RFMP2B, // 10
-                    Command::PRESB,  // 11
-                    Command::REFSB,  // 12
-                    Command::RFMSB,  // 13
-                    Command::PREAB,  // 14
-                    Command::REFAB,  // 15
-                    Command::RFMAB,  // 16
-                    Command::PDEA,   // 17
-                    Command::PDEP,   // 18
-                    Command::SREFEN, // 19
-                    Command::PDXA,   // 20
-                    Command::PDXP,   // 21
-                    Command::SREFEX  // 22
+                    Command::MWR,    // 3
+                    Command::RDA,    // 4
+                    Command::WRA,    // 5
+                    Command::MWRA,   // 6
+                    Command::ACT,    // 7
+                    Command::PREPB,  // 8
+                    Command::REFPB,  // 9
+                    Command::RFMPB,  // 10
+                    Command::REFP2B, // 11
+                    Command::RFMP2B, // 12
+                    Command::PRESB,  // 13
+                    Command::REFSB,  // 14
+                    Command::RFMSB,  // 15
+                    Command::PREAB,  // 16
+                    Command::REFAB,  // 17
+                    Command::RFMAB,  // 18
+                    Command::PDEA,   // 19
+                    Command::PDEP,   // 20
+                    Command::SREFEN, // 21
+                    Command::PDXA,   // 22
+                    Command::PDXP,   // 23
+                    Command::SREFEX  // 24
            };
    type = commandOfPhase[phase - BEGIN_NOP];
 }
@@ -117,26 +119,28 @@ std::string Command::toString() const
                    "NOP",      // 0
                    "RD",       // 1
                    "WR",       // 2
-                    "RDA",      // 3
-                    "WRA",      // 4
-                    "ACT",      // 5
-                    "PREPB",    // 6
-                    "REFPB",    // 7
-                    "RFMPB",    // 8
-                    "REFP2B",   // 9
-                    "RFMP2B",   // 10
-                    "PRESB",    // 11
-                    "REFSB",    // 12
-                    "RFMSB",    // 13
-                    "PREAB",    // 14
-                    "REFAB",    // 15
-                    "RFMAB",    // 16
-                    "PDEA",     // 17
-                    "PDEP",     // 18
-                    "SREFEN",   // 19
-                    "PDXA",     // 20
-                    "PDXP",     // 21
-                    "SREFEX"    // 22
+                    "MWR",      // 3
+                    "RDA",      // 4
+                    "WRA",      // 5
+                    "MWRA",     // 6
+                    "ACT",      // 7
+                    "PREPB",    // 8
+                    "REFPB",    // 9
+                    "RFMPB",    // 10
+                    "REFP2B",   // 11
+                    "RFMP2B",   // 12
+                    "PRESB",    // 13
+                    "REFSB",    // 14
+                    "RFMSB",    // 15
+                    "PREAB",    // 16
+                    "REFAB",    // 17
+                    "RFMAB",    // 18
+                    "PDEA",     // 19
+                    "PDEP",     // 20
+                    "SREFEN",   // 21
+                    "PDXA",     // 22
+                    "PDXP",     // 23
+                    "SREFEX"    // 24
            };
    return stringOfCommand[type];
 }
@@ -154,26 +158,28 @@ tlm_phase Command::toPhase() const
                    BEGIN_NOP,        // 0
                    BEGIN_RD,         // 1
                    BEGIN_WR,         // 2
-                    BEGIN_RDA,        // 3
-                    BEGIN_WRA,        // 4
-                    BEGIN_ACT,        // 5
-                    BEGIN_PREPB,      // 6
-                    BEGIN_REFPB,      // 7
-                    BEGIN_RFMPB,      // 8
-                    BEGIN_REFP2B,     // 9
-                    BEGIN_RFMP2B,     // 10
-                    BEGIN_PRESB,      // 11
-                    BEGIN_REFSB,      // 12
-                    BEGIN_RFMSB,      // 13
-                    BEGIN_PREAB,      // 14
-                    BEGIN_REFAB,      // 15
-                    BEGIN_RFMAB,      // 16
-                    BEGIN_PDNA,       // 17
-                    BEGIN_PDNP,       // 18
-                    BEGIN_SREF,       // 19
-                    END_PDNA,         // 20
-                    END_PDNP,         // 21
-                    END_SREF          // 22
+                    BEGIN_MWR,        // 3
+                    BEGIN_RDA,        // 4
+                    BEGIN_WRA,        // 5
+                    BEGIN_MWRA,       // 6
+                    BEGIN_ACT,        // 7
+                    BEGIN_PREPB,      // 8
+                    BEGIN_REFPB,      // 9
+                    BEGIN_RFMPB,      // 10
+                    BEGIN_REFP2B,     // 11
+                    BEGIN_RFMP2B,     // 12
+                    BEGIN_PRESB,      // 13
+                    BEGIN_REFSB,      // 14
+                    BEGIN_RFMSB,      // 15
+                    BEGIN_PREAB,      // 16
+                    BEGIN_REFAB,      // 17
+                    BEGIN_RFMAB,      // 18
+                    BEGIN_PDNA,       // 19
+                    BEGIN_PDNP,       // 20
+                    BEGIN_SREF,       // 21
+                    END_PDNA,         // 22
+                    END_PDNP,         // 23
+                    END_SREF          // 24
            };
    return phaseOfCommand[type];
 }
@@ -188,26 +194,28 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
                    MemCommand::NOP,        // 0
                    MemCommand::RD,         // 1
                    MemCommand::WR,         // 2
-                    MemCommand::RDA,        // 3
-                    MemCommand::WRA,        // 4
-                    MemCommand::ACT,        // 5
-                    MemCommand::PRE,        // 6, PREPB
-                    MemCommand::REFB,       // 7, REFPB
-                    MemCommand::NOP,        // 8, RFMPB
-                    MemCommand::NOP,        // 9, REFP2B
-                    MemCommand::NOP,        // 10, RFMP2B
-                    MemCommand::NOP,        // 11, PRESB
-                    MemCommand::NOP,        // 12, REFSB
-                    MemCommand::NOP,        // 13, RFMSB
-                    MemCommand::PREA,       // 14, PREAB
-                    MemCommand::REF,        // 15, REFAB
-                    MemCommand::NOP,        // 16, RFMAB
-                    MemCommand::PDN_S_ACT,  // 17
-                    MemCommand::PDN_S_PRE,  // 18
-                    MemCommand::SREN,       // 19
-                    MemCommand::PUP_ACT,    // 20
-                    MemCommand::PUP_PRE,    // 21
-                    MemCommand::SREX        // 22
+                    MemCommand::NOP,        // 3
+                    MemCommand::RDA,        // 4
+                    MemCommand::WRA,        // 5
+                    MemCommand::NOP,        // 6
+                    MemCommand::ACT,        // 7
+                    MemCommand::PRE,        // 8, PREPB
+                    MemCommand::REFB,       // 9, REFPB
+                    MemCommand::NOP,        // 10, RFMPB
+                    MemCommand::NOP,        // 11, REFP2B
+                    MemCommand::NOP,        // 12, RFMP2B
+                    MemCommand::NOP,        // 13, PRESB
+                    MemCommand::NOP,        // 14, REFSB
+                    MemCommand::NOP,        // 15, RFMSB
+                    MemCommand::PREA,       // 16, PREAB
+                    MemCommand::REF,        // 17, REFAB
+                    MemCommand::NOP,        // 18, RFMAB
+                    MemCommand::PDN_S_ACT,  // 19
+                    MemCommand::PDN_S_PRE,  // 20
+                    MemCommand::SREN,       // 21
+                    MemCommand::PUP_ACT,    // 22
+                    MemCommand::PUP_PRE,    // 23
+                    MemCommand::SREX        // 24
            };
    return phaseOfCommand[phase - BEGIN_NOP];
 }
@@ -240,7 +248,7 @@ bool Command::isRankCommand() const
 bool Command::isCasCommand() const
 {
    assert(type >= Command::NOP && type <= Command::SREFEX);
-    return (type <= Command::WRA);
+    return (type <= Command::MWRA);
 }

 bool Command::isRasCommand() const
--- a/src/libdramsys/DRAMSys/controller/Command.h
+++ b/src/libdramsys/DRAMSys/controller/Command.h
@@ -60,28 +60,30 @@ namespace DRAMSys
 DECLARE_EXTENDED_PHASE(BEGIN_NOP);    // 5
 DECLARE_EXTENDED_PHASE(BEGIN_RD);     // 6
 DECLARE_EXTENDED_PHASE(BEGIN_WR);     // 7
-DECLARE_EXTENDED_PHASE(BEGIN_RDA);    // 8
-DECLARE_EXTENDED_PHASE(BEGIN_WRA);    // 9
-DECLARE_EXTENDED_PHASE(BEGIN_ACT);    // 10
-DECLARE_EXTENDED_PHASE(BEGIN_PREPB);  // 11
-DECLARE_EXTENDED_PHASE(BEGIN_REFPB);  // 12
-DECLARE_EXTENDED_PHASE(BEGIN_RFMPB);  // 13
-DECLARE_EXTENDED_PHASE(BEGIN_REFP2B); // 14
-DECLARE_EXTENDED_PHASE(BEGIN_RFMP2B); // 15
-DECLARE_EXTENDED_PHASE(BEGIN_PRESB);  // 16
-DECLARE_EXTENDED_PHASE(BEGIN_REFSB);  // 17
-DECLARE_EXTENDED_PHASE(BEGIN_RFMSB);  // 18
-DECLARE_EXTENDED_PHASE(BEGIN_PREAB);  // 19
-DECLARE_EXTENDED_PHASE(BEGIN_REFAB);  // 20
-DECLARE_EXTENDED_PHASE(BEGIN_RFMAB);  // 21
+DECLARE_EXTENDED_PHASE(BEGIN_MWR);    // 8
+DECLARE_EXTENDED_PHASE(BEGIN_RDA);    // 9
+DECLARE_EXTENDED_PHASE(BEGIN_WRA);    // 10
+DECLARE_EXTENDED_PHASE(BEGIN_MWRA);   // 11
+DECLARE_EXTENDED_PHASE(BEGIN_ACT);    // 12
+DECLARE_EXTENDED_PHASE(BEGIN_PREPB);  // 13
+DECLARE_EXTENDED_PHASE(BEGIN_REFPB);  // 14
+DECLARE_EXTENDED_PHASE(BEGIN_RFMPB);  // 15
+DECLARE_EXTENDED_PHASE(BEGIN_REFP2B); // 16
+DECLARE_EXTENDED_PHASE(BEGIN_RFMP2B); // 17
+DECLARE_EXTENDED_PHASE(BEGIN_PRESB);  // 18
+DECLARE_EXTENDED_PHASE(BEGIN_REFSB);  // 19
+DECLARE_EXTENDED_PHASE(BEGIN_RFMSB);  // 20
+DECLARE_EXTENDED_PHASE(BEGIN_PREAB);  // 21
+DECLARE_EXTENDED_PHASE(BEGIN_REFAB);  // 22
+DECLARE_EXTENDED_PHASE(BEGIN_RFMAB);  // 23

-DECLARE_EXTENDED_PHASE(BEGIN_PDNA);   // 22
-DECLARE_EXTENDED_PHASE(BEGIN_PDNP);   // 23
-DECLARE_EXTENDED_PHASE(BEGIN_SREF);   // 24
+DECLARE_EXTENDED_PHASE(BEGIN_PDNA);   // 24
+DECLARE_EXTENDED_PHASE(BEGIN_PDNP);   // 25
+DECLARE_EXTENDED_PHASE(BEGIN_SREF);   // 26

-DECLARE_EXTENDED_PHASE(END_PDNA);     // 25
-DECLARE_EXTENDED_PHASE(END_PDNP);     // 26
-DECLARE_EXTENDED_PHASE(END_SREF);     // 27
+DECLARE_EXTENDED_PHASE(END_PDNA);     // 27
+DECLARE_EXTENDED_PHASE(END_PDNP);     // 28
+DECLARE_EXTENDED_PHASE(END_SREF);     // 29

 #ifdef DRAMPOWER
 DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
@@ -101,27 +103,29 @@ public:
        NOP = 0, // 0
        RD,      // 1
        WR,      // 2
-        RDA,     // 3
-        WRA,     // 4
-        ACT,     // 5
-        PREPB,   // 6
-        REFPB,   // 7
-        RFMPB,   // 8
-        REFP2B,  // 9
-        RFMP2B,  // 10
-        PRESB,   // 11
-        REFSB,   // 12
-        RFMSB,   // 13
-        PREAB,   // 14
-        REFAB,   // 15
-        RFMAB,   // 16
-        PDEA,    // 17
-        PDEP,    // 18
-        SREFEN,  // 19
-        PDXA,    // 20
-        PDXP,    // 21
-        SREFEX,  // 22
-        END_ENUM // 23, To mark the end of this enumeration
+        MWR,     // 3
+        RDA,     // 4
+        WRA,     // 5
+        MWRA,    // 6
+        ACT,     // 7
+        PREPB,   // 8
+        REFPB,   // 9
+        RFMPB,   // 10
+        REFP2B,  // 11
+        RFMP2B,  // 12
+        PRESB,   // 13
+        REFSB,   // 14
+        RFMSB,   // 15
+        PREAB,   // 16
+        REFAB,   // 17
+        RFMAB,   // 18
+        PDEA,    // 19
+        PDEP,    // 20
+        SREFEN,  // 21
+        PDXA,    // 22
+        PDXP,    // 23
+        SREFEX,  // 24
+        END_ENUM // 25, To mark the end of this enumeration
    };

 private:
--- a/src/libdramsys/DRAMSys/controller/Controller.cpp
+++ b/src/libdramsys/DRAMSys/controller/Controller.cpp
@@ -89,7 +89,7 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
 {
    SC_METHOD(controllerMethod);
    sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEvent;
-    
+
    ranksNumberOfPayloads = ControllerVector<Rank, unsigned>(memSpec.ranksPerChannel);

    // reserve buffer for command tuples
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
@@ -132,7 +132,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        assert(ControllerExtension::getBurstLength(payload) == 8);

--- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
@@ -49,7 +49,7 @@ CheckerDDR4::CheckerDDR4(const Configuration& config)
    memSpec = dynamic_cast<const MemSpecDDR4 *>(config.memSpec.get());
    if (memSpec == nullptr)
        SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen");
-    
+
    lastScheduledByCommandAndBank = std::vector<ControllerVector<Bank, sc_time>>
            (Command::numberOfCommands(), ControllerVector<Bank, sc_time>(memSpec->banksPerChannel, scMaxTime));
    lastScheduledByCommandAndBankGroup = std::vector<ControllerVector<BankGroup, sc_time>>
@@ -60,7 +60,7 @@ CheckerDDR4::CheckerDDR4(const Configuration& config)
    lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), scMaxTime);
    lastCommandOnBus = scMaxTime;
    last4Activates = ControllerVector<Rank, std::queue<sc_time>>(memSpec->ranksPerChannel);
-    
+
    tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
    tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE;
    tRDWR_R = memSpec->tRL + tBURST + memSpec->tRTRS - memSpec->tWL + memSpec->tWPRE;
@@ -78,7 +78,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic
    Rank rank = ControllerExtension::getRank(payload);
    BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
    Bank bank = ControllerExtension::getBank(payload);
-    
+
    sc_time lastCommandStart;
    sc_time earliestTimeToStart = sc_time_stamp();

@@ -153,7 +153,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        assert(ControllerExtension::getBurstLength(payload) == 8);

--- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp
@@ -79,7 +79,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi
    Rank rank = ControllerExtension::getRank(payload);
    BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
    Bank bank = ControllerExtension::getBank(payload);
-    
+
    sc_time lastCommandStart;
    sc_time earliestTimeToStart = sc_time_stamp();

@@ -154,7 +154,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generi
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        assert(ControllerExtension::getBurstLength(payload) == 8);

--- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp
@@ -79,7 +79,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener
    Rank rank = ControllerExtension::getRank(payload);
    BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
    Bank bank = ControllerExtension::getBank(payload);
-    
+
    sc_time lastCommandStart;
    sc_time earliestTimeToStart = sc_time_stamp();

@@ -156,7 +156,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_gener
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        unsigned burstLength = ControllerExtension::getBurstLength(payload);
        assert(!(memSpec->dataRate == 4) || (burstLength == 8)); // DDR mode (QDR wrt CK)
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp
@@ -78,7 +78,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi
    Rank rank = ControllerExtension::getRank(payload);
    BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
    Bank bank = ControllerExtension::getBank(payload);
-    
+
    sc_time lastCommandStart;
    sc_time earliestTimeToStart = sc_time_stamp();

@@ -153,7 +153,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generi
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tLK);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        assert(ControllerExtension::getBurstLength(payload) == 16);

--- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
@@ -136,7 +136,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        unsigned burstLength = ControllerExtension::getBurstLength(payload);
        assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2 || burstLength == 4)); // Legacy mode
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
@@ -136,7 +136,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        unsigned burstLength = ControllerExtension::getBurstLength(payload);
        assert((burstLength == 16) || (burstLength == 32));
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp
@@ -134,7 +134,7 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_gene
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        assert(ControllerExtension::getBurstLength(payload) == 8);

--- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp
@@ -130,7 +130,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_gener
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        unsigned burstLength = ControllerExtension::getBurstLength(payload);
        assert((burstLength == 2) || (burstLength == 4));
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp
@@ -131,7 +131,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_gene
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
    }
-    else if (command == Command::WR || command == Command::WRA)
+    else if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
    {
        unsigned burstLength = ControllerExtension::getBurstLength(payload);
        assert((burstLength == 4) || (burstLength == 8));
--- a/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
+++ b/src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
@@ -144,12 +144,42 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
        if (phase == BEGIN_RD || phase == BEGIN_RDA)
        {
            unsigned char* phyAddr = memory + trans.get_address();
-            memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
+
+            if (trans.get_byte_enable_ptr() == nullptr)
+            {
+                memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
+            }
+            else
+            {
+                for (std::size_t i = 0; i < trans.get_data_length(); i++)
+                {
+                    std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    {
+                        trans.get_data_ptr()[i] = phyAddr[i];
+                    }
+                }
+            }
        }
-        else if (phase == BEGIN_WR || phase == BEGIN_WRA)
+        else if (phase == BEGIN_WR || phase == BEGIN_WRA || phase == BEGIN_MWR || phase == BEGIN_MWRA)
        {
            unsigned char* phyAddr = memory + trans.get_address();
-            memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
+
+            if (trans.get_byte_enable_ptr() == nullptr)
+            {
+                memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
+            }
+            else
+            {
+                for (std::size_t i = 0; i < trans.get_data_length(); i++)
+                {
+                    std::size_t byteEnableIndex = i % trans.get_byte_enable_length();
+                    if (trans.get_byte_enable_ptr()[byteEnableIndex] != 0)
+                    {
+                        phyAddr[i] = trans.get_data_ptr()[i];
+                    }
+                }
+            }
        }
    }