Fix configuration tests

src/libdramsys/DRAMSys/simulation/DRAMSys.h

@@ -71,8 +71,10 @@ public:
     SC_HAS_PROCESS(DRAMSys);
     DRAMSys(const sc_core::sc_module_name& name, const Config::Configuration& config);
 
-    const MemSpec& getMemSpec() const { return *memSpec; }
-    const AddressDecoder& getAddressDecoder() const { return *addressDecoder; }
+    const auto& getSimConfig() const { return simConfig; }
+    const auto& getMcConfig() const { return mcConfig; }
+    const auto& getMemSpec() const { return *memSpec; }
+    const auto& getAddressDecoder() const { return *addressDecoder; }
 
     /**
      * Returns true if all memory controllers are in idle state.

tests/tests_configuration/reference.json

@@ -145,8 +145,6 @@
             "DatabaseRecording": true,
             "Debug": false,
             "EnableWindowing": false,
-            "ErrorCSVFile": "error.csv",
-            "ErrorChipSeed": 42,
             "PowerAnalysis": false,
             "SimulationName": "ddr5",
             "SimulationProgressBar": true,
@@ -207,4 +205,4 @@
             }
         ]
     }
-}
+}

tests/tests_configuration/resources/simconfig/ddr5.json

@@ -6,8 +6,6 @@
         "Debug": false,
         "ECCControllerMode": "Disabled",
         "EnableWindowing": false,
-        "ErrorCSVFile": "",
-        "ErrorChipSeed": 42,
         "PowerAnalysis": false,
         "SimulationName": "ddr5",
         "SimulationProgressBar": true,

tests/tests_configuration/test_configuration.cpp

@@ -166,7 +166,11 @@ DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
         {"clkMhz", 1600},
     }}};
 
-    return {memArchitectureSpec, "JEDEC_2x8x2Gbx4_DDR5-3200A", "DDR5", memTimingSpec, {}};
+    return {memArchitectureSpec,
+            "JEDEC_2x8x2Gbx4_DDR5-3200A",
+            DRAMSys::Config::MemoryType::DDR5,
+            memTimingSpec,
+            {}};
 }
 
 DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer()
@@ -317,8 +321,6 @@ TEST_F(ConfigurationTest, SimConfig)
                     "DatabaseRecording": true,
                     "Debug": false,
                     "EnableWindowing": false,
-                    "ErrorCSVFile": "error.csv",
-                    "ErrorChipSeed": 42,
                     "PowerAnalysis": false,
                     "SimulationName": "ddr5",
                     "SimulationProgressBar": true,

tests/tests_dramsys/b_transport/b_transport.cpp

@@ -92,7 +92,7 @@ struct BlockingInitiator : sc_core::sc_module
         sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
         iSocket->b_transport(payload, delay);
 
-        EXPECT_EQ(delay, dramSys.getConfig().blockingReadDelay);
+        EXPECT_EQ(delay, dramSys.getMcConfig().blockingReadDelay);
     }
 
     void writeAccess()
@@ -105,7 +105,7 @@ struct BlockingInitiator : sc_core::sc_module
         sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
         iSocket->b_transport(payload, delay);
 
-        EXPECT_EQ(delay, dramSys.getConfig().blockingWriteDelay);
+        EXPECT_EQ(delay, dramSys.getMcConfig().blockingWriteDelay);
     }
 };
 

tests/tests_dramsys/b_transport/configs/no_storage.json

@@ -138,8 +138,6 @@
             "DatabaseRecording": true,
             "Debug": false,
             "EnableWindowing": false,
-            "ErrorCSVFile": "",
-            "ErrorChipSeed": 42,
             "PowerAnalysis": false,
             "SimulationName": "example",
             "SimulationProgressBar": true,
@@ -150,4 +148,4 @@
         },
         "simulationid": "ddr4-example"
     }
-}
+}

tests/tests_dramsys/b_transport/configs/storage.json

@@ -136,8 +136,6 @@
             "DatabaseRecording": true,
             "Debug": false,
             "EnableWindowing": false,
-            "ErrorCSVFile": "",
-            "ErrorChipSeed": 42,
             "PowerAnalysis": false,
             "SimulationName": "example",
             "SimulationProgressBar": true,
@@ -148,4 +146,4 @@
         },
         "simulationid": "ddr4-example"
     }
-}
+}