Jonathan Hager
d773abc7ce
Updated unit tests for HBM2
...
This is necessary, as recording the phases with tlmRecorders on the bus
changed the internal call order in the SystemC kernel. This leads to
different IDs in the database
2025-03-26 13:53:23 +01:00
Jonathan Hager
9c690c021c
Fixed nullptr segfault if no database recording
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Dram and Controller handle this case now and are initialized with a
shared_ptr pointing to null
2025-03-26 13:53:22 +01:00
Jonathan Hager
2f8c318c0e
Implemented b_transport and dbg
2025-03-26 13:53:22 +01:00
Jonathan Hager
d349aafff7
Change TlmRecorderArbiter to TlmRecorderController
2025-03-26 13:53:22 +01:00
Jonathan Hager
86281cc6d3
Removed ControllerRecordable
2025-03-26 13:53:22 +01:00
Jonathan Hager
5b7dcbcc1c
Moved TlmRecorder from reference to smart pointer
2025-03-26 13:53:22 +01:00
Jonathan Hager
0479184f72
Split the bandwidth recording in two modules
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This allows separate recording of the bandwidth between Arbiter -
Controller and Controller - Dram
2025-03-26 13:53:22 +01:00
Jonathan Hager
f1445ab851
WIP: Moved BufferDepth out of ControllerRecordable
2025-03-26 13:53:22 +01:00
Jonathan Hager
9a563e78d5
Moved Bandwidth recording out of the Controller
2025-03-26 13:53:22 +01:00
Jonathan Hager
c45137958d
Removed DramRecordable
2025-03-26 13:53:11 +01:00
Jonathan Hager
d5862e55ea
Moved DramRecordable logic to Dram
2025-03-26 13:52:19 +01:00
Jonathan Hager
0975e52f5f
Changed TlmRecorderWrapper to simple_sockets
2025-03-26 13:52:19 +01:00
Jonathan Hager
8b64cbf047
Added TlmRecorderWrapper to handle database logic
2025-03-26 13:52:18 +01:00
c1f4655d19
Fix delays in traffic generators
2025-03-26 09:59:51 +01:00
98eae7fcf4
Fix the forward declaration of the Dram class
2025-03-25 19:18:09 +01:00
aafb704cf8
Use std::optional in cmdMux
2025-03-24 13:39:50 +01:00
e9643e7938
Fix issue with stack id
2025-03-03 16:58:51 +01:00
76e8dba113
Do not align address to minimum burst length
2025-02-26 17:10:11 +01:00
5b76e52cd4
Do not create empty database file when it does not exist
2025-02-26 09:28:36 +01:00
6861576550
Implement tCCDR for HBM2 and fix bug with SID
2025-02-21 14:18:30 +01:00
b9fc47d1fe
When project is top-level, force C++17
2025-02-13 11:14:55 +01:00
Lukas Steiner
f223e6c500
Merge branch 'feat/hbm3_sid' into 'develop'
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Feat/hbm3 sid
See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
e57ce9cc86
Use controller clock as interface clock in initiators
2025-01-24 15:55:40 +01:00
581794b970
Allow responses to be sent back-to-back
2025-01-24 14:58:06 +01:00
ba94d9fd84
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
0a478dbdc5
Issue a warning if ThinkDelayFw is 0
2025-01-24 14:18:40 +01:00
007c55e878
Use think delay as miminum END_REQ delay
...
When the controller accepts requests in the same clock cycle as it
handles them, undeterministic simulations can occur as the outcome
depends on if the new request is accepted before the controllerMethod
is called or not.
Therefore, a minimum delay of one clock cylce should be used to always
handle request only in the next clock cycle, removing the disambiguity.
2025-01-24 14:18:39 +01:00
Lukas Steiner
1b50709591
Merge branch 'feat/new_checkers' into 'develop'
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Use new timing checkers
See merge request ems/astdm/modeling.dram/dram.sys.5!95
2025-01-17 14:23:24 +00:00
d71e649447
Fix the verification of generator parameters
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Also, clamp the read write ratio instead of generating an error
2025-01-14 14:55:11 +01:00
7a8633d36e
Implement stack ID for HBM3
2025-01-13 15:36:05 +01:00
ed709b82d4
Integrate new Timing Checker
2025-01-13 10:24:08 +01:00
marcomoerz
5b52015c75
changed namespace
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DRAMSys::DRAMPower to DRAMPower::DRAMPower
2025-01-10 14:08:50 +01:00
83cc41e318
Minor refactorings of CMakeList files
2025-01-09 08:12:49 +00:00
6d6c8c595f
Clean up private/public linking
2024-12-20 17:40:16 +01:00
ffc94a73cb
Update dependency versions
2024-12-20 17:40:15 +01:00
e2342350d0
Minor improvements on package handling
2024-12-20 17:40:15 +01:00
c3eb5e6a62
Hide the use of FetchContent behind a flag
...
FetchContent is now disabled by default, when the project is included as
an subproject by another top-level project.
Also, every usage of FetchContent is behind a separate flag to enable and
disable the usage with granular control.
2024-12-20 17:40:15 +01:00
ca9ef16d0d
Remove unnecessary project() calls
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project() should only be called if the subdirectory, in fact, can be
built standalone.
2024-12-20 17:40:15 +01:00
e1b8bbf12d
Clean up and refactor CMakeLists
2024-12-20 17:40:15 +01:00
91a09ad771
Use FindQwt.cmake script
2024-12-20 17:40:15 +01:00
ac69d25003
Fix CMake deprecation warning
2024-12-20 17:40:15 +01:00
a37171c6fd
Remove file globs from CMakeLists
...
Fix build
2024-12-20 17:40:15 +01:00
703ee81d7e
Introduce SimulationTime config
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Use SimulationTime to forcefully stop simulation at a specified point in
time.
2024-12-10 10:04:59 +01:00
Lukas Steiner
be1807e9b0
Merge branch 'fix/buffer_entries' into 'develop'
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Fix/buffer entries
Closes #64
See merge request ems/astdm/modeling.dram/dram.sys.5!86
2024-11-29 10:34:09 +00:00
Lukas Steiner
01caf7875e
Merge branch 'fix/bandwidth' into 'develop'
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Fix for bandwidth calculations with pseudo-channels
See merge request ems/astdm/modeling.dram/dram.sys.5!87
2024-11-29 08:48:37 +00:00
f960f499c6
Improve TA performance by increasing window of loaded transactions
2024-11-18 13:48:06 +01:00
e409bab47a
Implement pseudo-channel and rank specific BW information
2024-11-18 13:18:33 +01:00
e74a617273
Crude fix for bandwidth calculations with pseudo-channels
2024-11-15 15:57:37 +01:00
18c00fc363
Pass a number of required buffer entries to hasBufferSpace()
2024-11-15 14:17:03 +01:00
ad1ea86d2e
Fix the data burst location when a think delay is set
2024-11-05 11:04:24 +01:00
