Have a one cycle END_RESP delay in the standard initiator
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@@ -131,7 +131,7 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload& payload, const tlm::tl
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else if (phase == tlm::BEGIN_RESP)
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{
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tlm::tlm_phase nextPhase = tlm::END_RESP;
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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sc_core::sc_time delay = clkPeriod;
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iSocket->nb_transport_fw(payload, nextPhase, delay);
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payload.release();
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tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb
LFS
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BIN
tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb
LFS
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