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Merge branch 'feat/new_checkers' into 'develop'

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Use new timing checkers

See merge request ems/astdm/modeling.dram/dram.sys.5!95
This commit is contained in:
Lukas Steiner
2025-01-17 14:23:24 +00:00
parent e5ca7f1229 a82efdbb3a
commit 1b50709591
16 changed files with 17905 additions and 4938 deletions
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2024
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp
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src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,14 +29,16 @@
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef CHECKERDDR3_H
#define CHECKERDDR3_H
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
#include <queue>
#include <vector>
@@ -47,35 +49,37 @@ namespace DRAMSys
class CheckerDDR3 final : public CheckerIF
{
public:
explicit CheckerDDR3(const MemSpecDDR3 &memSpec);
[[nodiscard]] sc_core::sc_time
timeToSatisfyConstraints(Command command,
const tlm::tlm_generic_payload& payload) const override;
explicit CheckerDDR3(const MemSpecDDR3& memSpec);
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecDDR3& memSpec;
std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<ControllerVector<Rank, sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
ControllerVector<Rank, std::queue<sc_core::sc_time>> last4Activates;
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tWRPRE;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
template<typename T>
using CommandArray = std::array<T, Command::END_ENUM>;
template<typename T>
using BankVector = ControllerVector<Bank, T>;
template<typename T>
using RankVector = ControllerVector<Rank, T>;
CommandArray<BankVector<sc_core::sc_time>> nextCommandByBank;
CommandArray<RankVector<sc_core::sc_time>> nextCommandByRank;
RankVector<std::queue<sc_core::sc_time>> last4ActivatesOnRank;
sc_core::sc_time nextCommandOnBus = sc_core::SC_ZERO_TIME;
};
} // namespace DRAMSys
#endif // CHECKERDDR3_H
#endif // CHECKERDDR3_H

2325
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp
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src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,18 @@
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef CHECKERDDR4_H
#define CHECKERDDR4_H
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
#include <queue>
#include <unordered_map>
#include <utility>
#include <vector>
namespace DRAMSys
@@ -50,24 +50,12 @@ class CheckerDDR4 final : public CheckerIF
{
public:
explicit CheckerDDR4(const MemSpecDDR4& memSpec);
[[nodiscard]] sc_core::sc_time
timeToSatisfyConstraints(Command command,
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecDDR4& memSpec;
std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<ControllerVector<BankGroup, sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<ControllerVector<Rank, sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
// Four activate window
ControllerVector<Rank, std::queue<sc_core::sc_time>> last4Activates;
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
@@ -80,8 +68,24 @@ private:
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
template<typename T>
using CommandArray = std::array<T, Command::END_ENUM>;
template<typename T>
using BankVector = ControllerVector<Bank, T>;
template<typename T>
using BankGroupVector = ControllerVector<BankGroup, T>;
template<typename T>
using RankVector = ControllerVector<Rank, T>;
CommandArray<BankVector<sc_core::sc_time>> nextCommandByBank;
CommandArray<BankGroupVector<sc_core::sc_time>> nextCommandByBankGroup;
CommandArray<RankVector<sc_core::sc_time>> nextCommandByRank;
RankVector<std::queue<sc_core::sc_time>> last4ActivatesOnRank;
sc_core::sc_time nextCommandOnBus = sc_core::SC_ZERO_TIME;
};
} // namespace DRAMSys
#endif // CHECKERDDR4_H
#endif // CHECKERDDR4_H

1770
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp
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src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,14 +29,16 @@
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef CHECKERHBM2_H
#define CHECKERHBM2_H
#include "DRAMSys/configuration/memspec/MemSpecHBM2.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecHBM2.h"
#include <queue>
#include <vector>
@@ -48,39 +50,40 @@ class CheckerHBM2 final : public CheckerIF
{
public:
explicit CheckerHBM2(const MemSpecHBM2& memSpec);
[[nodiscard]] sc_core::sc_time
timeToSatisfyConstraints(Command command,
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecHBM2& memSpec;
std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<ControllerVector<BankGroup, sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<ControllerVector<Rank, sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnRasBus;
sc_core::sc_time lastCommandOnCasBus;
// Four activate window
ControllerVector<Rank, std::queue<sc_core::sc_time>> last4Activates;
ControllerVector<Rank, unsigned> bankwiseRefreshCounter;
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
sc_core::sc_time tBURST;
sc_core::sc_time tRDPDE;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRPDE;
sc_core::sc_time tWRAPDE;
sc_core::sc_time tRTWR;
sc_core::sc_time tWRRDS;
sc_core::sc_time tWRRDL;
sc_core::sc_time tWRRDR;
template<typename T>
using CommandArray = std::array<T, Command::END_ENUM>;
template<typename T>
using BankVector = ControllerVector<Bank, T>;
template<typename T>
using BankGroupVector = ControllerVector<BankGroup, T>;
template<typename T>
using RankVector = ControllerVector<Rank, T>;
CommandArray<BankVector<sc_core::sc_time>> nextCommandByBank;
CommandArray<BankGroupVector<sc_core::sc_time>> nextCommandByBankGroup;
CommandArray<RankVector<sc_core::sc_time>> nextCommandByRank;
RankVector<std::queue<sc_core::sc_time>> last4ActivatesOnRank;
ControllerVector<Rank, unsigned> bankwiseRefreshCounter;
sc_core::sc_time nextCommandOnRasBus = sc_core::SC_ZERO_TIME;
sc_core::sc_time nextCommandOnCasBus = sc_core::SC_ZERO_TIME;
};
} // namespace DRAMSys
#endif // CHECKERHBM2_H
#endif // CHECKERHBM2_H

2451
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
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src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,14 +29,16 @@
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef CHECKERLPDDR4_H
#define CHECKERLPDDR4_H
#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h"
#include "DRAMSys/controller/checker/CheckerIF.h"
#include "DRAMSys/configuration/memspec/MemSpecLPDDR4.h"
#include <queue>
#include <vector>
@@ -48,35 +50,20 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
explicit CheckerLPDDR4(const MemSpecLPDDR4& memSpec);
[[nodiscard]] sc_core::sc_time
timeToSatisfyConstraints(Command command,
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecLPDDR4& memSpec;
std::vector<ControllerVector<Bank, sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<ControllerVector<Rank, sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
ControllerVector<Command, ControllerVector<Bank, uint8_t>> lastBurstLengthByCommandAndBank;
// Four activate window
ControllerVector<Rank, std::queue<sc_core::sc_time>> last4Activates;
const sc_core::sc_time scMaxTime = sc_core::sc_max_time();
sc_core::sc_time tBURST;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDPRE;
sc_core::sc_time tRDAPRE;
sc_core::sc_time tRDAACT;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRAPRE;
sc_core::sc_time tWRAACT;
sc_core::sc_time tACTPDEN;
sc_core::sc_time tPRPDEN;
@@ -84,8 +71,21 @@ private:
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
sc_core::sc_time tREFPDEN;
template<typename T>
using CommandArray = std::array<T, Command::END_ENUM>;
template<typename T>
using BankVector = ControllerVector<Bank, T>;
template<typename T>
using RankVector = ControllerVector<Rank, T>;
CommandArray<BankVector<sc_core::sc_time>> nextCommandByBank;
CommandArray<RankVector<sc_core::sc_time>> nextCommandByRank;
RankVector<std::queue<sc_core::sc_time>> last4ActivatesOnRank;
sc_core::sc_time nextCommandOnBus = sc_core::SC_ZERO_TIME;
};
} // namespace DRAMSys
#endif // CHECKERLPDDR4_H
#endif // CHECKERLPDDR4_H