Updated unit tests for HBM2

This is necessary, as recording the phases with tlmRecorders on the bus
changed the internal call order in the SystemC kernel. This leads to
different IDs in the database

src/libdramsys/DRAMSys/simulation/DRAMSys.cpp

@@ -165,6 +165,8 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name, const Config::Configuratio
     }
 
     // Connect all internal DRAMSys modules:
+    // If database recording is enabled, then the tlmRecorders are placed
+    // on the bus between the modules
     tSocket.bind(arbiter->tSocket);
     for (unsigned i = 0; i < memSpec->numberOfChannels; i++)
     {
@@ -176,6 +178,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name, const Config::Configuratio
         }
         else if (simConfig.checkTLM2Protocol)
         {
+            // Arbiter <--> tlmRecorder <--> Controller
             arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
             controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
         }
@@ -189,14 +192,15 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name, const Config::Configuratio
             arbiter->iSocket.bind(controllers[i]->tSocket);
         }
 
-        // TODO: comments
         if (simConfig.databaseRecording)
         {
+            // Controller <--> tlmRecorder <--> Dram
             controllers[i]->iSocket.bind(tlmRecordersDram[i]->tSocket);
             tlmRecordersDram[i]->iSocket.bind(drams[i]->tSocket);
         }
         else
         {
+            // Controller <--> Dram
             controllers[i]->iSocket.bind(drams[i]->tSocket);
         }
     }