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Author SHA1 Message Date
Lukas Steiner (2)
7934d2e160 Renaming libDRAMPowerIF to libDRAMPowerDummy. 2019-08-26 16:26:28 +02:00
Lukas Steiner
2402180a9c Merge branch 'DRAMSys4.0_ctrl' of https://git.eit.uni-kl.de/ems/astdm/dram.sys into DRAMSys4.0_ctrl 2019-08-25 23:14:19 +02:00
Lukas Steiner
d4943bccc5 Debug Manager cleanup. 2019-08-25 23:13:05 +02:00
Lukas Steiner (2)
98c52b8a3e Merge remote-tracking branch 'origin/master' into DRAMSys4.0_ctrl 
# Conflicts:
#	DRAMSys/library/src/simulation/MemoryManager.cpp
 2019-08-23 09:54:56 +02:00
Matthias Jung
f6072e9d4f Fixed Memory Leak 
As pointed out by @sprado, there was a memory leak in the STL player.
The data pointer was allocated, but never deleted again. Some lines for
deletion were commented out in the memory manager in the free function.
These two lines regarding the deletion of data were moved into the
destructor of the memory manager. The allocation of the data is done in
the allocate() function of the memory manager when a new payload is
generated.
 2019-08-22 23:11:48 +02:00
Matthias Jung
d55d801a04 Merge branch 'master' of https://git.eit.uni-kl.de/ems/astdm/dram.sys 2019-08-22 23:03:05 +02:00
Matthias Jung
a6f679b86b Add compile flag for macOS 2019-08-22 23:00:38 +02:00
Matthias Jung
9702d7a8f3 Add compile flag for macOS 2019-08-22 22:59:23 +02:00
Matthias Jung
6388b3d75c DRAM command was not set in trace recorder 2019-08-22 22:40:28 +02:00
Lukas Steiner
f5f3c729e0 Temporary fix of memory leak. 2019-08-22 22:16:33 +02:00
Lukas Steiner (2)
1fc5f3bf88 Some phase renaming in TraceAnalyzer. 2019-08-20 14:56:45 +02:00
Lukas Steiner (2)
4881b8ae76 Implemented initial version of timing checker for WideIO. 2019-08-20 10:58:28 +02:00
Lukas Steiner (2)
2ef1c2b189 Removed RefreshCheckerIF, RefreshCheckerDummy is now used as base class. 2019-08-20 10:11:56 +02:00
Lukas Steiner (2)
baa976dac4 Removed unused commands and extended protocol phases. 2019-08-20 09:51:55 +02:00
Lukas Steiner (2)
cbeaef32de Removed specific memspec dependency in RefreshManager, changed RefreshChecker to RefreshCheckerDDR3. 2019-08-19 16:17:31 +02:00
Lukas Steiner (2)
7c87b954ec Removed different refresh timings for different banks, removed ORGR parameters from mcconfigs. 2019-08-19 15:11:49 +02:00
Lukas Steiner (2)
35af025d4c Removed unused configuration parameters, moved some currents and voltages to specific memspecs. 2019-08-19 13:51:27 +02:00
Lukas Steiner (2)
3f7296f2a5 Removed RGR timing parameters. 2019-08-19 11:16:27 +02:00
Lukas Steiner
8115aba222 Fixed wrong PRE -<> PREA test in TraceAnalyzer. 2019-08-18 19:56:17 +02:00
Lukas Steiner
4d936892d9 Included DRAMPower dummy, it can now be switched on and off again. 2019-08-18 19:23:53 +02:00
Lukas Steiner (2)
7b8bb86620 Removed old timing parameters, moved DramPower configuration to specific Drams. 2019-08-15 14:55:55 +02:00
Lukas Steiner
7d675a9837 Renaming and minor improvements. 2019-08-14 21:19:42 +02:00
Lukas Steiner
31101a0827 Finished bankwise refresh. 2019-08-14 20:19:27 +02:00
Lukas Steiner (2)
47ee187bc3 Working on RefreshManagerBankwise. 2019-08-14 13:48:04 +02:00
Lukas Steiner (2)
0918a78648 Included GenericController for polymorphism. 2019-08-14 09:44:24 +02:00
Lukas Steiner (2)
c2022667c5 Included files for RefreshManagerBankwise. 2019-08-13 14:23:44 +02:00
Lukas Steiner (2)
3b26997ea4 Updated structure of RefreshManager for bankwise refresh implementation. 2019-08-13 11:39:15 +02:00
Lukas Steiner (2)
38a099b8e8 Included RefreshChecker for different refresh modes. 2019-08-12 16:41:44 +02:00
Lukas Steiner (2)
e6dc4e7c75 Removed unused files of old controller. 2019-08-12 14:19:22 +02:00
Lukas Steiner
05a8272ee6 Moved bandwidth calculation to GenericController. 2019-08-10 01:01:52 +02:00
Lukas Steiner
dc194781f7 Code formatting. 2019-08-09 23:46:49 +02:00
Lukas Steiner
08dc5e811a Removed redundant check in controllerMethod. 2019-08-09 23:45:17 +02:00
Lukas Steiner (2)
1dea807da3 Included various events to avoid multiple triggers of controllerMethod at the same time. 2019-08-09 19:38:49 +02:00
Lukas Steiner (2)
2e40894097 Included RefreshManagerIF and RefreshManagerDummy to disable refresh. 2019-08-09 13:39:02 +02:00
Lukas Steiner (2)
1bd322e576 Fixed "PREA if all banks are precharged" issue. 2019-08-09 10:35:17 +02:00
Lukas Steiner (2)
88f57dd88f Included refresh. 2019-08-08 16:22:33 +02:00
Lukas Steiner (2)
ca36faa403 Changed printDebugMessage into macro to turn it off completely for speedup. 2019-08-08 09:45:22 +02:00
Lukas Steiner (2)
c93a11fbf5 Code formatting. 2019-08-02 10:44:49 +02:00
Lukas Steiner (2)
85e9fc6930 Included bandwidth calculation. Fixed bug (RD/WR from wrong row). 2019-08-01 16:26:57 +02:00
Lukas Steiner (2)
6a66c89130 Included GenericController for verilator compatibility. 2019-08-01 11:00:31 +02:00
Lukas Steiner (2)
36373c9cce Gave all sc_modules names. Added missing virtual destructors in different DRAMs. 2019-07-31 15:20:13 +02:00
Lukas Steiner (2)
ed96f9fb54 Added new CheckerDDR3, changed checker type in controller to CheckerIF for polymorphism. 2019-07-30 16:25:05 +02:00
Lukas Steiner (2)
1053f7c1b7 Created CheckerIF, removed old CheckerDDR3. 2019-07-30 16:03:49 +02:00
Lukas Steiner (2)
b9f0c31ddf Moved controller state into timing checker. Inserted preambles. 2019-07-30 15:14:24 +02:00
Lukas Steiner (2)
b477424a98 Bugfix: Commands on one bank can overlap now. 2019-07-30 13:30:59 +02:00
Lukas Steiner
fb9abb9cee Changed type of payloadID to uint64_t for overflow prevention. 2019-07-29 20:55:40 +02:00
Lukas Steiner (2)
4fa59c2410 Included ControllerRecordable for disabling of trace recording. 2019-07-29 16:44:14 +02:00
Lukas Steiner (2)
91755962a2 Improvement in timing checker: additional map instead of for loops. 2019-07-29 14:17:03 +02:00
Lukas Steiner (2)
de650810dd Changed interface of scheduler, small bugfix (wrong debug message in Controller). 2019-07-29 11:05:03 +02:00
Lukas Steiner
dbcdf3f61d Included FAW check. 2019-07-28 22:53:27 +02:00