Lukas Steiner
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08dc5e811a
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Removed redundant check in controllerMethod.
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2019-08-09 23:45:17 +02:00 |
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Lukas Steiner (2)
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1dea807da3
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Included various events to avoid multiple triggers of controllerMethod at the same time.
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2019-08-09 19:38:49 +02:00 |
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Lukas Steiner (2)
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2e40894097
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Included RefreshManagerIF and RefreshManagerDummy to disable refresh.
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2019-08-09 13:39:02 +02:00 |
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Lukas Steiner (2)
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1bd322e576
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Fixed "PREA if all banks are precharged" issue.
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2019-08-09 10:35:17 +02:00 |
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Lukas Steiner (2)
|
88f57dd88f
|
Included refresh.
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2019-08-08 16:22:33 +02:00 |
|
Lukas Steiner (2)
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ca36faa403
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Changed printDebugMessage into macro to turn it off completely for speedup.
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2019-08-08 09:45:22 +02:00 |
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Lukas Steiner (2)
|
c93a11fbf5
|
Code formatting.
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2019-08-02 10:44:49 +02:00 |
|
Lukas Steiner (2)
|
85e9fc6930
|
Included bandwidth calculation. Fixed bug (RD/WR from wrong row).
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2019-08-01 16:26:57 +02:00 |
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Lukas Steiner (2)
|
6a66c89130
|
Included GenericController for verilator compatibility.
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2019-08-01 11:00:31 +02:00 |
|
Lukas Steiner (2)
|
36373c9cce
|
Gave all sc_modules names. Added missing virtual destructors in different DRAMs.
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2019-07-31 15:20:13 +02:00 |
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Lukas Steiner (2)
|
ed96f9fb54
|
Added new CheckerDDR3, changed checker type in controller to CheckerIF for polymorphism.
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2019-07-30 16:25:05 +02:00 |
|
Lukas Steiner (2)
|
1053f7c1b7
|
Created CheckerIF, removed old CheckerDDR3.
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2019-07-30 16:03:49 +02:00 |
|
Lukas Steiner (2)
|
b9f0c31ddf
|
Moved controller state into timing checker. Inserted preambles.
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2019-07-30 15:14:24 +02:00 |
|
Lukas Steiner (2)
|
b477424a98
|
Bugfix: Commands on one bank can overlap now.
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2019-07-30 13:30:59 +02:00 |
|
Lukas Steiner
|
fb9abb9cee
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Changed type of payloadID to uint64_t for overflow prevention.
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2019-07-29 20:55:40 +02:00 |
|
Lukas Steiner (2)
|
4fa59c2410
|
Included ControllerRecordable for disabling of trace recording.
|
2019-07-29 16:44:14 +02:00 |
|
Lukas Steiner (2)
|
91755962a2
|
Improvement in timing checker: additional map instead of for loops.
|
2019-07-29 14:17:03 +02:00 |
|
Lukas Steiner (2)
|
de650810dd
|
Changed interface of scheduler, small bugfix (wrong debug message in Controller).
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2019-07-29 11:05:03 +02:00 |
|
Lukas Steiner
|
dbcdf3f61d
|
Included FAW check.
|
2019-07-28 22:53:27 +02:00 |
|
Lukas Steiner
|
42344ce87f
|
Removed lastDataStrobeCommands in ControllerState, removed unused methods in timing checker.
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2019-07-28 21:50:28 +02:00 |
|
Lukas Steiner
|
a05b0ed610
|
Removed RowBufferState in ControllerState.
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2019-07-28 20:57:48 +02:00 |
|
Lukas Steiner
|
e0743b71d6
|
Small improvement in ControllerNew (redundant event triggers), renaming in ControllerState.
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2019-07-28 20:45:03 +02:00 |
|
Lukas Steiner
|
733525e787
|
Included command mux which selects the oldest payload and a command mux interface.
|
2019-07-27 21:12:22 +02:00 |
|
Lukas Steiner
|
215790a931
|
Created different schedulers (Fifo and FrFcfs) and a scheduler interface.
|
2019-07-27 19:24:09 +02:00 |
|
Lukas Steiner (2)
|
c4c2640594
|
Moved event trigger out of BankMachine.
|
2019-07-26 16:28:22 +02:00 |
|
Lukas Steiner (2)
|
3f913b5c16
|
Arbiter now assigns each payload an ID for transaction order decision in CommandMux.
|
2019-07-26 15:48:58 +02:00 |
|
Lukas Steiner (2)
|
f2ab2fe3ee
|
Included first test for CommandMux.
|
2019-07-25 16:40:03 +02:00 |
|
Lukas Steiner (2)
|
38a21088a0
|
Merge branch 'master' into DRAMSys4.0_ctrl
|
2019-07-25 13:47:57 +02:00 |
|
Matthias Jung
|
7304055a22
|
Merge branch 'googletest_merge2' into 'master'
Include googletest and subproject for unit tests.
See merge request ems/astdm/dram.sys!240
|
2019-07-25 12:02:33 +02:00 |
|
Lukas Steiner (2)
|
a303f242e6
|
Included googletest and subproject for unit tests.
|
2019-07-25 11:49:18 +02:00 |
|
Lukas Steiner
|
7bd0950e1e
|
Some minor changes.
|
2019-07-23 21:30:29 +02:00 |
|
Lukas Steiner (2)
|
e1e53b5c2e
|
Moved parts of logic from CommandMux::selectCommand to controlMethod, moved commandFinishedTime from BMs to Controller.
|
2019-07-23 16:20:38 +02:00 |
|
Lukas Steiner (2)
|
1e8b8e37ea
|
Moved if statements from inner methods to controllerMethod().
|
2019-07-23 15:10:19 +02:00 |
|
Lukas Steiner (2)
|
e7552f6916
|
Code cleanup.
|
2019-07-23 14:30:01 +02:00 |
|
Lukas Steiner (2)
|
0d0c7415b2
|
Fixed clk cycle waiting for fifo strict transaction order.
|
2019-07-23 14:13:51 +02:00 |
|
Lukas Steiner
|
6aa2533edd
|
New controller is working.
|
2019-07-22 20:31:17 +02:00 |
|
Lukas Steiner
|
f69771e7be
|
Simulation is running to the end, results may still be wrong.
|
2019-07-22 17:59:51 +02:00 |
|
Lukas Steiner
|
1ce8996ece
|
Some bugs are fixed, still not running.
|
2019-07-22 01:53:18 +02:00 |
|
Lukas Steiner
|
ef011ad52c
|
Ready for debugging.
|
2019-07-22 00:23:12 +02:00 |
|
Lukas Steiner
|
9204a88a28
|
Included some functionality, included scheduler.
|
2019-07-20 23:32:37 +02:00 |
|
Lukas Steiner (2)
|
cd5b5cb423
|
Included new controller classes.
|
2019-07-20 15:53:30 +02:00 |
|
Lukas Steiner (2)
|
41e2db0b5a
|
Removed refresh and power down.
|
2019-07-19 10:29:14 +02:00 |
|
Lukas Steiner (2)
|
f43ea71e95
|
Minor changes in new timing checker.
|
2019-07-16 15:52:02 +02:00 |
|
Lukas Steiner (2)
|
be83ad01cb
|
Included remaining commands.
|
2019-07-11 15:22:09 +02:00 |
|
Lukas Steiner (2)
|
9be64edaa9
|
Added commands ACT, PRE, PREA, RD, RDA, WR, WRA, PDEA, PDEP to new timing checker.
|
2019-07-10 15:55:45 +02:00 |
|
Lukas Steiner (2)
|
3e4e8e9408
|
Included new timing checker for DDR3.
|
2019-07-09 15:52:09 +02:00 |
|
Lukas Steiner (2)
|
cb393b8abf
|
Renaming of commands, TODOs in timing checkers.
|
2019-07-05 16:17:52 +02:00 |
|
Lukas Steiner (2)
|
37b2dc9e4d
|
Renaming of commands according to DRAMml.
|
2019-07-04 10:13:19 +02:00 |
|
Lukas Steiner (2)
|
34626448bb
|
RefMode (tRFC) is now only configurable during initialization.
|
2019-07-02 16:25:43 +02:00 |
|
Lukas Steiner (2)
|
41cc447d86
|
Included timing parameters for RGR.
|
2019-07-02 14:25:53 +02:00 |
|