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90aab2f926de720acbdc82b927f719fe5a10cbba
gem5/src/sim
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Daniel R. Carvalho 90aab2f926 sim: Rename ProbePoints namespace as probing 
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ProbePoints became ::probing.

"probing" was chosen over "probe_points" because the
namespace contains more than solely probe points; it
contains all classes related to the act of probing.

Change-Id: I44567974a521707593739a2bd5933391803e5b51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45412
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
..
guest_abi
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
power
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
probe
sim: Rename ProbePoints namespace as probing
2021-05-29 11:13:49 +00:00
async.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
async.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
aux_vector.hh
base: Add GEM5_DEPRECATED_ENUM_VAL
2021-05-19 15:55:29 +00:00
backtrace_glibc.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
backtrace_none.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
backtrace.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
byteswap.hh
sim: Use type_traits to steer swap_bytes.
2021-05-11 20:15:10 +00:00
byteswap.test.cc
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
clock_domain.cc
base-stats: Rename Units namespace as units
2021-05-26 22:30:33 +00:00
clock_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ClockDomain.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
clocked_object.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
clocked_object.hh
misc: Rename SimClock namespace as sim_clock
2021-05-26 22:30:33 +00:00
ClockedObject.py
sim-power: Creation of PowerState class
2020-04-29 21:03:31 +00:00
core.cc
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
core.hh
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
cur_tick.cc
sim: Move cur tick to its own files
2021-02-03 01:12:27 +00:00
cur_tick.hh
sim: Move cur tick to its own files
2021-02-03 01:12:27 +00:00
cxx_config_ini.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config_ini.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
cxx_manager.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
cxx_manager.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
debug.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
debug.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
drain.cc
misc: Collapse all uses of DTRACE(x) to Debug::x.
2021-05-10 20:00:48 +00:00
drain.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
dvfs_handler.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
dvfs_handler.hh
misc: Fix coding style for struct's opening braces
2021-03-19 20:57:24 +00:00
DVFSHandler.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
emul_driver.hh
dev-hsa: enable interruptible hsa signal support
2021-01-31 03:25:05 +00:00
eventq.cc
misc: Collapse all uses of DTRACE(x) to Debug::x.
2021-05-10 20:00:48 +00:00
eventq.hh
misc: Collapse all uses of DTRACE(x) to Debug::x.
2021-05-10 20:00:48 +00:00
faults.cc
sim: Trap into GDB instead of panicking on SEGV
2021-04-22 11:14:30 +00:00
faults.hh
arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
2021-04-17 22:39:37 +00:00
fd_array.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
fd_array.hh
sim: Generalize the arrayParamOut and arrayParamIn functions.
2020-10-22 22:00:38 +00:00
fd_entry.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
fd_entry.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
full_system.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
futex_map.cc
sim-se: don't wake up SE futex syscalls on ARM events
2020-08-10 08:52:03 +00:00
futex_map.hh
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
global_event.cc
misc: Make many includes explicit.
2020-06-03 19:42:46 +00:00
global_event.hh
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
guest_abi.hh
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
guest_abi.test.cc
sim: Fix test names in guest ABI unit test
2021-05-27 12:26:19 +00:00
init_signals.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
init_signals.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
init.cc
misc: Replace M5_LOCAL and M5_WEAK with GEM5_LOCAL and GEM5_WEAK.
2021-05-11 20:16:31 +00:00
init.hh
ext: Update pybind11 to version 2.6.2.
2021-02-02 06:26:03 +00:00
insttracer.hh
sim: Don't needlessly recreate ISA types in InstRecord.
2021-04-20 00:14:09 +00:00
InstTracer.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
kernel_workload.cc
sim: Add a copied symbol table for the kernel on physical address
2021-03-18 13:44:18 +00:00
kernel_workload.hh
misc: Use PARAMS
2021-02-19 23:27:34 +00:00
linear_solver.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
linear_solver.hh
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
main.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
mathexpr.cc
sim: Add function that returns all variables in a MathExpr
2020-04-29 21:02:32 +00:00
mathexpr.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
mem_pool.cc
sim: Add pool specific allocators to SE mode
2021-04-22 20:01:33 +00:00
mem_pool.hh
sim: Add pool specific allocators to SE mode
2021-04-22 20:01:33 +00:00
mem_state.cc
mem,sim: Get the page size from the page table in SE mode.
2020-11-06 08:16:40 +00:00
mem_state.hh
misc: Clean up ISA switching header includes.
2021-05-28 23:41:03 +00:00
port.cc
sim: Add some helpers to catch and reporting using unbound ports.
2020-06-16 02:35:41 +00:00
port.hh
sim: Add some helpers to catch and reporting using unbound ports.
2020-06-16 02:35:41 +00:00
power_domain.cc
base-stats: Rename Units namespace as units
2021-05-26 22:30:33 +00:00
power_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
power_state.cc
base-stats: Rename Units namespace as units
2021-05-26 22:30:33 +00:00
power_state.hh
misc: Use PARAMS
2021-02-19 23:27:34 +00:00
PowerDomain.py
sim-power: Addition of PowerDomains
2020-04-29 21:03:31 +00:00
PowerState.py
sim-power: Addition of PowerDomains
2020-04-29 21:03:31 +00:00
process_impl.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
process.cc
misc: Clean up ISA switching header includes.
2021-05-28 23:41:03 +00:00
process.hh
arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
2021-05-07 19:36:08 +00:00
Process.py
sim: Consistently use ISO prefixes
2021-01-24 18:45:01 +00:00
proxy_ptr.hh
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
proxy_ptr.test.cc
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
pseudo_inst.cc
misc: Clean up ISA switching header includes.
2021-05-28 23:41:03 +00:00
pseudo_inst.hh
arch,sim: Rename PseudoInst namespace as pseudo_inst
2021-05-26 23:08:21 +00:00
py_interact.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
py_interact.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
python.cc
ext: Update pybind11 to version 2.6.2.
2021-02-02 06:26:03 +00:00
redirect_path.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
redirect_path.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
RedirectPath.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
root.cc
misc: Rename SimClock namespace as sim_clock
2021-05-26 22:30:33 +00:00
root.hh
sim,systemc: Use slightly non-standard constructors for custom create()
2021-03-11 07:34:10 +00:00
Root.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
SConscript
sim: Add pool specific allocators to SE mode
2021-04-22 20:01:33 +00:00
SConsopts
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
se_signal.cc
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
se_signal.hh
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
se_workload.cc
misc: Use PARAMS
2021-02-19 23:27:34 +00:00
se_workload.hh
misc: Remove unused params() definitions
2021-02-19 23:27:34 +00:00
serialize_handlers.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
serialize.cc
sim: Move SimObjectResolver dependency to SimObject
2021-03-18 17:34:30 +00:00
serialize.hh
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
sim_events.cc
base: Clean up base/hostinfo
2021-02-19 16:40:22 +00:00
sim_events.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
sim_exit.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
sim_object.cc
sim: Move SimObjectResolver dependency to SimObject
2021-03-18 17:34:30 +00:00
sim_object.hh
sim: Move SimObjectResolver dependency to SimObject
2021-03-18 17:34:30 +00:00
simulate.cc
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
simulate.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stat_control.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
stat_control.hh
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
stat_register.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stat_register.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stats.cc
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
stats.hh
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
sub_system.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
sub_system.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SubSystem.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_abi.hh
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
syscall_debug_macros.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_desc.cc
misc: Remove the "fault" parameter from syscall functions.
2020-09-02 03:30:20 +00:00
syscall_desc.hh
arch,sim: Rename GuestABI namespace as guest_abi
2021-05-26 23:08:21 +00:00
syscall_emul_buf.hh
sim: Make PortProxy args in BaseBufferArg const ref.
2021-05-29 05:34:46 +00:00
syscall_emul.cc
misc: Clean up ISA switching header includes.
2021-05-28 23:41:03 +00:00
syscall_emul.hh
arch,kern,sim: Use a map to map syscall flags.
2021-05-28 00:46:56 +00:00
syscall_return.hh
sim: Make SyscallReturn handle extra/"pseudo" return registers.
2020-03-12 01:35:34 +00:00
system.cc
arch,base,sim: Construct the GDB stub with no threads.
2021-05-28 07:56:19 +00:00
system.hh
sim,cpu: Move the remote GDB stub into the workload.
2021-05-28 07:56:19 +00:00
System.py
sim: Create a Workload object for SE mode.
2020-09-20 07:26:22 +00:00
ticked_object.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
ticked_object.hh
misc: Fix mismatched struct/class "tags" and reenable that warning.
2021-02-19 08:29:00 +00:00
TickedObject.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
vma.cc
misc: Clean up ISA switching header includes.
2021-05-28 23:41:03 +00:00
vma.hh
misc: Replace some includes of arch/isa_traits.hh.
2020-08-25 03:22:22 +00:00
voltage_domain.cc
base-stats: Rename Units namespace as units
2021-05-26 22:30:33 +00:00
voltage_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
VoltageDomain.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
workload.cc
arch,base,sim: Move GDB stub creation into the arch Workloads.
2021-05-28 07:56:19 +00:00
workload.hh
arch,base,sim: Move GDB stub creation into the arch Workloads.
2021-05-28 07:56:19 +00:00
Workload.py
sim,cpu: Move the remote GDB stub into the workload.
2021-05-28 07:56:19 +00:00