misc: Delete the now unnecessary create methods.

Most create() methods are no longer necessary. This change deletes them,
and occasionally moves some code from them into the constructors they
call.

Change-Id: Icbab29ba280144b892f9b12fac9e29a0839477e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

@@ -202,15 +202,3 @@ CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
 }
 
 } // namespace FastModel
-
-FastModel::CortexA76 *
-FastModelCortexA76Params::create() const
-{
-    return new FastModel::CortexA76(*this);
-}
-
-FastModel::CortexA76Cluster *
-FastModelCortexA76ClusterParams::create() const
-{
-    return new FastModel::CortexA76Cluster(*this);
-}

src/arch/arm/fastmodel/CortexA76/evs.cc

@@ -153,27 +153,3 @@ template class ScxEvsCortexA76<ScxEvsCortexA76x3Types>;
 template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
 
 } // namespace FastModel
-
-FastModel::ScxEvsCortexA76x1 *
-FastModelScxEvsCortexA76x1Params::create() const
-{
-    return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexA76x2 *
-FastModelScxEvsCortexA76x2Params::create() const
-{
-    return new FastModel::ScxEvsCortexA76x2(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexA76x3 *
-FastModelScxEvsCortexA76x3Params::create() const
-{
-    return new FastModel::ScxEvsCortexA76x3(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexA76x4 *
-FastModelScxEvsCortexA76x4Params::create() const
-{
-    return new FastModel::ScxEvsCortexA76x4(name.c_str(), *this);
-}

src/arch/arm/fastmodel/CortexA76/evs.hh

@@ -93,6 +93,7 @@ class ScxEvsCortexA76 : public Types::Base
     const Params &params;
 
   public:
+    ScxEvsCortexA76(const Params &p) : ScxEvsCortexA76(p.name.c_str(), p) {}
     ScxEvsCortexA76(const sc_core::sc_module_name &mod_name, const Params &p);
 
     void before_end_of_elaboration() override;

src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

@@ -160,15 +160,3 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
 }
 
 } // namespace FastModel
-
-FastModel::CortexR52 *
-FastModelCortexR52Params::create() const
-{
-    return new FastModel::CortexR52(*this);
-}
-
-FastModel::CortexR52Cluster *
-FastModelCortexR52ClusterParams::create() const
-{
-    return new FastModel::CortexR52Cluster(*this);
-}

src/arch/arm/fastmodel/CortexR52/evs.cc

@@ -129,27 +129,3 @@ template class ScxEvsCortexR52<ScxEvsCortexR52x3Types>;
 template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
 
 } // namespace FastModel
-
-FastModel::ScxEvsCortexR52x1 *
-FastModelScxEvsCortexR52x1Params::create() const
-{
-    return new FastModel::ScxEvsCortexR52x1(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexR52x2 *
-FastModelScxEvsCortexR52x2Params::create() const
-{
-    return new FastModel::ScxEvsCortexR52x2(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexR52x3 *
-FastModelScxEvsCortexR52x3Params::create() const
-{
-    return new FastModel::ScxEvsCortexR52x3(name.c_str(), *this);
-}
-
-FastModel::ScxEvsCortexR52x4 *
-FastModelScxEvsCortexR52x4Params::create() const
-{
-    return new FastModel::ScxEvsCortexR52x4(name.c_str(), *this);
-}

src/arch/arm/fastmodel/CortexR52/evs.hh

@@ -117,6 +117,7 @@ class ScxEvsCortexR52 : public Types::Base
     const Params &params;
 
   public:
+    ScxEvsCortexR52(const Params &p) : ScxEvsCortexR52(p.name.c_str(), p) {}
     ScxEvsCortexR52(const sc_core::sc_module_name &mod_name, const Params &p);
 
     void

src/arch/arm/fastmodel/GIC/gic.cc

@@ -358,15 +358,3 @@ GIC::supportsVersion(GicVersion version)
 }
 
 } // namespace FastModel
-
-FastModel::SCGIC *
-SCFastModelGICParams::create() const
-{
-    return new FastModel::SCGIC(*this, name.c_str());
-}
-
-FastModel::GIC *
-FastModelGICParams::create() const
-{
-    return new FastModel::GIC(*this);
-}

src/arch/arm/fastmodel/GIC/gic.hh

@@ -83,6 +83,7 @@ class SCGIC : public scx_evs_GIC
     const SCFastModelGICParams &_params;
 
   public:
+    SCGIC(const SCFastModelGICParams &p) : SCGIC(p, p.name.c_str()) {}
     SCGIC(const SCFastModelGICParams &params, sc_core::sc_module_name _name);
 
     SignalInterruptInitiatorSocket signalInterrupt;

src/arch/arm/fastmodel/iris/SConscript

@@ -32,7 +32,6 @@ SimObject('Iris.py')
 Source('cpu.cc')
 Source('interrupts.cc')
 Source('isa.cc')
-Source('mmu.cc')
 Source('tlb.cc')
 
 Source('thread_context.cc')

src/arch/arm/fastmodel/iris/interrupts.cc

@@ -106,9 +106,3 @@ void
 Iris::Interrupts::unserialize(CheckpointIn &cp)
 {
 }
-
-Iris::Interrupts *
-IrisInterruptsParams::create() const
-{
-    return new Iris::Interrupts(*this);
-}

src/arch/arm/fastmodel/iris/isa.cc

@@ -40,9 +40,3 @@ Iris::ISA::serialize(CheckpointOut &cp) const
         miscRegs[i] = tc->readMiscRegNoEffect(i);
     SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
 }
-
-Iris::ISA *
-IrisISAParams::create() const
-{
-    return new Iris::ISA(*this);
-}

src/arch/arm/fastmodel/iris/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/arm/fastmodel/iris/mmu.hh"
-
-Iris::MMU *
-IrisMMUParams::create() const
-{
-    return new Iris::MMU(*this);
-}

src/arch/arm/fastmodel/iris/tlb.cc

@@ -65,9 +65,3 @@ Iris::TLB::translateTiming(const RequestPtr &req, ::ThreadContext *tc,
     assert(translation);
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
-
-Iris::TLB *
-IrisTLBParams::create() const
-{
-    return new Iris::TLB(*this);
-}

src/arch/arm/freebsd/fs_workload.cc

@@ -126,9 +126,3 @@ FsFreebsd::~FsFreebsd()
 }
 
 } // namespace ArmISA
-
-ArmISA::FsFreebsd *
-ArmFsFreebsdParams::create() const
-{
-    return new ArmISA::FsFreebsd(*this);
-}

src/arch/arm/freebsd/se_workload.cc

@@ -154,9 +154,3 @@ EmuFreebsd::syscall(ThreadContext *tc)
 }
 
 } // namespace ArmISA
-
-ArmISA::EmuFreebsd *
-ArmEmuFreebsdParams::create() const
-{
-    return new ArmISA::EmuFreebsd(*this);
-}

src/arch/arm/fs_workload.cc

@@ -157,9 +157,3 @@ FsWorkload::getBootLoader(Loader::ObjectFile *const obj)
 }
 
 } // namespace ArmISA
-
-ArmISA::FsWorkload *
-ArmFsWorkloadParams::create() const
-{
-    return new ArmISA::FsWorkload(*this);
-}

src/arch/arm/interrupts.cc

@@ -39,12 +39,6 @@
 
 #include "arch/arm/system.hh"
 
-ArmISA::Interrupts *
-ArmInterruptsParams::create() const
-{
-    return new ArmISA::Interrupts(*this);
-}
-
 bool
 ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
 {

src/arch/arm/isa.cc

@@ -2487,9 +2487,3 @@ ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
 }
 
 }  // namespace ArmISA
-
-ArmISA::ISA *
-ArmISAParams::create() const
-{
-    return new ArmISA::ISA(*this);
-}

src/arch/arm/kvm/arm_cpu.cc

@@ -841,9 +841,3 @@ ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings)
             warn("Unhandled VFP register: 0x%x\n", id);
     }
 }
-
-ArmKvmCPU *
-ArmKvmCPUParams::create() const
-{
-    return new ArmKvmCPU(*this);
-}

src/arch/arm/kvm/armv8_cpu.cc

@@ -395,9 +395,3 @@ ArmV8KvmCPU::getSysRegMap() const
 
     return sysRegMap;
 }
-
-ArmV8KvmCPU *
-ArmV8KvmCPUParams::create() const
-{
-    return new ArmV8KvmCPU(*this);
-}

src/arch/arm/kvm/gic.cc

@@ -425,9 +425,3 @@ MuxingKvmGic::fromKvmToGicV2()
        assert((cpuPriority[cpu] & ~0xff) == 0);
     }
 }
-
-MuxingKvmGic *
-MuxingKvmGicParams::create() const
-{
-    return new MuxingKvmGic(*this);
-}

src/arch/arm/linux/fs_workload.cc

@@ -358,9 +358,3 @@ DumpStats::process(ThreadContext *tc)
 }
 
 } // namespace ArmISA
-
-ArmISA::FsLinux *
-ArmFsLinuxParams::create() const
-{
-    return new ArmISA::FsLinux(*this);
-}

src/arch/arm/linux/se_workload.cc

@@ -863,9 +863,3 @@ EmuLinux::syscall(ThreadContext *tc)
 }
 
 } // namespace ArmISA
-
-ArmISA::EmuLinux *
-ArmEmuLinuxParams::create() const
-{
-    return new ArmISA::EmuLinux(*this);
-}

src/arch/arm/mmu.cc

@@ -66,9 +66,3 @@ MMU::invalidateMiscReg(TLBType type)
         getDTBPtr()->invalidateMiscReg();
     }
 }
-
-ArmISA::MMU *
-ArmMMUParams::create() const
-{
-    return new ArmISA::MMU(*this);
-}

src/arch/arm/nativetrace.cc

@@ -219,13 +219,3 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
 }
 
 } // namespace Trace
-
-////////////////////////////////////////////////////////////////////////
-//
-//  ExeTracer Simulation Object
-//
-Trace::ArmNativeTrace *
-ArmNativeTraceParams::create() const
-{
-    return new Trace::ArmNativeTrace(*this);
-}

src/arch/arm/pmu.cc

@@ -807,9 +807,3 @@ PMU::SWIncrementEvent::write(uint64_t val)
 }
 
 } // namespace ArmISA
-
-ArmISA::PMU *
-ArmPMUParams::create() const
-{
-    return new ArmISA::PMU(*this);
-}

src/arch/arm/semihosting.cc

@@ -1043,10 +1043,3 @@ operator << (std::ostream &os, const ArmSemihosting::InPlaceArg &ipa)
     ccprintf(os, "[%#x-%#x)", ipa.addr, ipa.addr + ipa.size - 1);
     return os;
 }
-
-
-ArmSemihosting *
-ArmSemihostingParams::create() const
-{
-    return new ArmSemihosting(*this);
-}

src/arch/arm/stage2_mmu.cc

@@ -140,9 +140,3 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault,
         event->process();
     }
 }
-
-ArmISA::Stage2MMU *
-ArmStage2MMUParams::create() const
-{
-    return new ArmISA::Stage2MMU(*this);
-}

src/arch/arm/system.cc

@@ -234,9 +234,3 @@ ArmSystem::callClearWakeRequest(ThreadContext *tc)
     if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
         pwr_ctrl->clearWakeRequest(tc);
 }
-
-ArmSystem *
-ArmSystemParams::create() const
-{
-    return new ArmSystem(*this);
-}

src/arch/arm/table_walker.cc

@@ -2251,12 +2251,6 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
     }
 }
 
-ArmISA::TableWalker *
-ArmTableWalkerParams::create() const
-{
-    return new ArmISA::TableWalker(*this);
-}
-
 LookupLevel
 TableWalker::toLookupLevel(uint8_t lookup_level_as_int)
 {

src/arch/arm/tlb.cc

@@ -1692,10 +1692,3 @@ TLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
                                domain, lookup_level);
     }
 }
-
-
-ArmISA::TLB *
-ArmTLBParams::create() const
-{
-    return new ArmISA::TLB(*this);
-}

src/arch/arm/tracers/tarmac_parser.cc

@@ -1363,9 +1363,3 @@ TarmacParserRecord::iSetStateToStr(ISetState isetstate) const
 }
 
 } // namespace Trace
-
-Trace::TarmacParser *
-TarmacParserParams::create() const
-{
-    return new Trace::TarmacParser(*this);
-}

src/arch/arm/tracers/tarmac_tracer.cc

@@ -93,9 +93,3 @@ TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
 }
 
 } // namespace Trace
-
-Trace::TarmacTracer *
-TarmacTracerParams::create() const
-{
-    return new Trace::TarmacTracer(*this);
-}

src/arch/mips/SConscript

@@ -38,7 +38,6 @@ if env['TARGET_ISA'] == 'mips':
     Source('isa.cc')
     Source('linux/linux.cc')
     Source('linux/se_workload.cc')
-    Source('mmu.cc')
     Source('pagetable.cc')
     Source('process.cc')
     Source('remote_gdb.cc')

src/arch/mips/interrupts.cc

@@ -184,9 +184,3 @@ Interrupts::interruptsPending() const
 }
 
 }
-
-MipsISA::Interrupts *
-MipsInterruptsParams::create() const
-{
-    return new MipsISA::Interrupts(*this);
-}

src/arch/mips/isa.cc

@@ -568,9 +568,3 @@ ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
 }
 
 }
-
-MipsISA::ISA *
-MipsISAParams::create() const
-{
-    return new MipsISA::ISA(*this);
-}

src/arch/mips/linux/se_workload.cc

@@ -477,9 +477,3 @@ SyscallDescTable<MipsISA::SEWorkload::SyscallABI> EmuLinux::syscallDescs = {
 };
 
 } // namespace MipsISA
-
-MipsISA::EmuLinux *
-MipsEmuLinuxParams::create() const
-{
-    return new MipsISA::EmuLinux(*this);
-}

src/arch/mips/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/mips/mmu.hh"
-
-MipsISA::MMU *
-MipsMMUParams::create() const
-{
-    return new MipsISA::MMU(*this);
-}

src/arch/mips/tlb.cc

@@ -256,9 +256,3 @@ TLB::index(bool advance)
 
     return *pte;
 }
-
-MipsISA::TLB *
-MipsTLBParams::create() const
-{
-    return new MipsISA::TLB(*this);
-}

src/arch/power/SConscript

@@ -40,10 +40,8 @@ if env['TARGET_ISA'] == 'power':
     Source('insts/floating.cc')
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
-    Source('interrupts.cc')
     Source('linux/linux.cc')
     Source('linux/se_workload.cc')
-    Source('mmu.cc')
     Source('isa.cc')
     Source('pagetable.cc')
     Source('process.cc')

src/arch/power/interrupts.cc

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/power/interrupts.hh"
-
-PowerISA::Interrupts *
-PowerInterruptsParams::create() const
-{
-    return new PowerISA::Interrupts(*this);
-}

src/arch/power/isa.cc

@@ -54,10 +54,3 @@ ISA::params() const
 }
 
 }
-
-PowerISA::ISA *
-PowerISAParams::create() const
-{
-    return new PowerISA::ISA(*this);
-}
-

src/arch/power/linux/se_workload.cc

@@ -448,9 +448,3 @@ SyscallDescTable<PowerISA::SEWorkload::SyscallABI> EmuLinux::syscallDescs = {
 };
 
 } // namespace PowerISA
-
-PowerISA::EmuLinux *
-PowerEmuLinuxParams::create() const
-{
-    return new PowerISA::EmuLinux(*this);
-}

src/arch/power/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/power/mmu.hh"
-
-PowerISA::MMU *
-PowerMMUParams::create() const
-{
-    return new PowerISA::MMU(*this);
-}

src/arch/power/tlb.cc

@@ -278,9 +278,3 @@ TLB::index(bool advance)
 
     return *pte;
 }
-
-PowerISA::TLB *
-PowerTLBParams::create() const
-{
-    return new PowerISA::TLB(*this);
-}

src/arch/riscv/SConscript

@@ -46,9 +46,7 @@ if env['TARGET_ISA'] == 'riscv':
     Source('decoder.cc')
     Source('faults.cc')
     Source('isa.cc')
-    Source('interrupts.cc')
     Source('locked_mem.cc')
-    Source('mmu.cc')
     Source('process.cc')
     Source('pagetable.cc')
     Source('pagetable_walker.cc')

src/arch/riscv/bare_metal/fs_workload.cc

@@ -69,9 +69,3 @@ BareMetal::initState()
 }
 
 } // namespace RiscvISA
-
-RiscvISA::BareMetal *
-RiscvBareMetalParams::create() const
-{
-    return new RiscvISA::BareMetal(*this);
-}

src/arch/riscv/interrupts.cc

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/riscv/interrupts.hh"
-
-RiscvISA::Interrupts *
-RiscvInterruptsParams::create() const
-{
-    return new RiscvISA::Interrupts(*this);
-}

src/arch/riscv/isa.cc

@@ -411,9 +411,3 @@ ISA::unserialize(CheckpointIn &cp)
 }
 
 }
-
-RiscvISA::ISA *
-RiscvISAParams::create() const
-{
-    return new RiscvISA::ISA(*this);
-}

src/arch/riscv/linux/se_workload.cc

@@ -783,9 +783,3 @@ SyscallDescTable<SEWorkload::SyscallABI> EmuLinux::syscallDescs32 = {
 };
 
 } // namespace RiscvISA
-
-RiscvISA::EmuLinux *
-RiscvEmuLinuxParams::create() const
-{
-    return new RiscvISA::EmuLinux(*this);
-}

src/arch/riscv/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/riscv/mmu.hh"
-
-RiscvISA::MMU *
-RiscvMMUParams::create() const
-{
-    return new RiscvISA::MMU(*this);
-}

src/arch/riscv/pagetable_walker.cc

@@ -579,9 +579,3 @@ Walker::WalkerState::pageFault(bool present)
 }
 
 } /* end namespace RiscvISA */
-
-RiscvISA::Walker *
-RiscvPagetableWalkerParams::create() const
-{
-    return new RiscvISA::Walker(*this);
-}

src/arch/riscv/tlb.cc

@@ -512,9 +512,3 @@ TLB::TlbStats::TlbStats(Stats::Group *parent)
         read_accesses + write_accesses)
 {
 }
-
-RiscvISA::TLB *
-RiscvTLBParams::create() const
-{
-    return new TLB(*this);
-}

src/arch/sparc/SConscript

@@ -33,12 +33,10 @@ if env['TARGET_ISA'] == 'sparc':
     Source('decoder.cc')
     Source('faults.cc')
     Source('fs_workload.cc')
-    Source('interrupts.cc')
     Source('isa.cc')
     Source('linux/linux.cc')
     Source('linux/se_workload.cc')
     Source('linux/syscalls.cc')
-    Source('mmu.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
     Source('process.cc')

src/arch/sparc/fs_workload.cc

@@ -50,9 +50,3 @@ FsWorkload::initState()
 }
 
 } // namespace SparcISA
-
-SparcISA::FsWorkload *
-SparcFsWorkloadParams::create() const
-{
-    return new SparcISA::FsWorkload(*this);
-}

src/arch/sparc/interrupts.cc

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2008 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/interrupts.hh"
-
-SparcISA::Interrupts *
-SparcInterruptsParams::create() const
-{
-    return new SparcISA::Interrupts(*this);
-}

src/arch/sparc/isa.cc

@@ -759,9 +759,3 @@ ISA::unserialize(CheckpointIn &cp)
 }
 
 }
-
-SparcISA::ISA *
-SparcISAParams::create() const
-{
-    return new SparcISA::ISA(*this);
-}

src/arch/sparc/linux/se_workload.cc

@@ -137,9 +137,3 @@ EmuLinux::syscall(ThreadContext *tc)
 }
 
 } // namespace SparcISA
-
-SparcISA::EmuLinux *
-SparcEmuLinuxParams::create() const
-{
-    return new SparcISA::EmuLinux(*this);
-}

src/arch/sparc/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/mmu.hh"
-
-SparcISA::MMU *
-SparcMMUParams::create() const
-{
-    return new SparcISA::MMU(*this);
-}

src/arch/sparc/nativetrace.cc

@@ -87,13 +87,3 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record)
 }
 
 } // namespace Trace
-
-////////////////////////////////////////////////////////////////////////
-//
-//  ExeTracer Simulation Object
-//
-Trace::SparcNativeTrace *
-SparcNativeTraceParams::create() const
-{
-    return new Trace::SparcNativeTrace(*this);
-};

src/arch/sparc/tlb.cc

@@ -1507,9 +1507,3 @@ TLB::unserialize(CheckpointIn &cp)
 }
 
 } // namespace SparcISA
-
-SparcISA::TLB *
-SparcTLBParams::create() const
-{
-    return new SparcISA::TLB(*this);
-}

src/arch/x86/SConscript

@@ -58,7 +58,6 @@ Source('insts/microregop.cc')
 Source('insts/static_inst.cc')
 Source('interrupts.cc')
 Source('isa.cc')
-Source('mmu.cc')
 Source('nativetrace.cc')
 Source('pagetable.cc')
 Source('pagetable_walker.cc')

src/arch/x86/bios/acpi.cc

@@ -68,21 +68,3 @@ X86ISA::ACPI::RSDT::RSDT(const Params &p) :
 X86ISA::ACPI::XSDT::XSDT(const Params &p) :
     SysDescTable(p, "XSDT", 1), entries(p.entries)
 {}
-
-X86ISA::ACPI::RSDP *
-X86ACPIRSDPParams::create() const
-{
-    return new X86ISA::ACPI::RSDP(*this);
-}
-
-X86ISA::ACPI::RSDT *
-X86ACPIRSDTParams::create() const
-{
-    return new X86ISA::ACPI::RSDT(*this);
-}
-
-X86ISA::ACPI::XSDT *
-X86ACPIXSDTParams::create() const
-{
-    return new X86ISA::ACPI::XSDT(*this);
-}

src/arch/x86/bios/e820.cc

@@ -70,15 +70,3 @@ void X86ISA::E820Table::writeTo(PortProxy& proxy, Addr countAddr, Addr addr)
         writeVal(entries[i]->type, proxy, addr);
     }
 }
-
-E820Table *
-X86E820TableParams::create() const
-{
-    return new E820Table(*this);
-}
-
-E820Entry *
-X86E820EntryParams::create() const
-{
-    return new E820Entry(*this);
-}

src/arch/x86/bios/intelmp.cc

@@ -150,12 +150,6 @@ X86ISA::IntelMP::FloatingPointer::FloatingPointer(const Params &p) :
     defaultConfig(p.default_config), imcrPresent(p.imcr_present)
 {}
 
-X86ISA::IntelMP::FloatingPointer *
-X86IntelMPFloatingPointerParams::create() const
-{
-    return new X86ISA::IntelMP::FloatingPointer(*this);
-}
-
 Addr
 X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy,
         Addr addr, uint8_t &checkSum)
@@ -253,12 +247,6 @@ X86ISA::IntelMP::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
     baseEntries(p.base_entries), extEntries(p.ext_entries)
 {}
 
-X86ISA::IntelMP::ConfigTable *
-X86IntelMPConfigTableParams::create() const
-{
-    return new X86ISA::IntelMP::ConfigTable(*this);
-}
-
 Addr
 X86ISA::IntelMP::Processor::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -290,12 +278,6 @@ X86ISA::IntelMP::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
     replaceBits(cpuSignature, 11, 8, p.family);
 }
 
-X86ISA::IntelMP::Processor *
-X86IntelMPProcessorParams::create() const
-{
-    return new X86ISA::IntelMP::Processor(*this);
-}
-
 Addr
 X86ISA::IntelMP::Bus::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -310,12 +292,6 @@ X86ISA::IntelMP::Bus::Bus(const Params &p) : BaseConfigEntry(p, 1),
     busID(p.bus_id), busType(p.bus_type)
 {}
 
-X86ISA::IntelMP::Bus *
-X86IntelMPBusParams::create() const
-{
-    return new X86ISA::IntelMP::Bus(*this);
-}
-
 Addr
 X86ISA::IntelMP::IOAPIC::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -335,12 +311,6 @@ X86ISA::IntelMP::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
         flags |= 1;
 }
 
-X86ISA::IntelMP::IOAPIC *
-X86IntelMPIOAPICParams::create() const
-{
-    return new X86ISA::IntelMP::IOAPIC(*this);
-}
-
 Addr
 X86ISA::IntelMP::IntAssignment::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -361,24 +331,12 @@ X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(const Params &p) :
             p.dest_io_apic_id, p.dest_io_apic_intin)
 {}
 
-X86ISA::IntelMP::IOIntAssignment *
-X86IntelMPIOIntAssignmentParams::create() const
-{
-    return new X86ISA::IntelMP::IOIntAssignment(*this);
-}
-
 X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(const Params &p) :
     IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 4,
             p.source_bus_id, p.source_bus_irq,
             p.dest_local_apic_id, p.dest_local_apic_intin)
 {}
 
-X86ISA::IntelMP::LocalIntAssignment *
-X86IntelMPLocalIntAssignmentParams::create() const
-{
-    return new X86ISA::IntelMP::LocalIntAssignment(*this);
-}
-
 Addr
 X86ISA::IntelMP::AddrSpaceMapping::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -397,12 +355,6 @@ X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(const Params &p) :
     addr(p.address), addrLength(p.length)
 {}
 
-X86ISA::IntelMP::AddrSpaceMapping *
-X86IntelMPAddrSpaceMappingParams::create() const
-{
-    return new X86ISA::IntelMP::AddrSpaceMapping(*this);
-}
-
 Addr
 X86ISA::IntelMP::BusHierarchy::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -426,12 +378,6 @@ X86ISA::IntelMP::BusHierarchy::BusHierarchy(const Params &p) :
         info |= 1;
 }
 
-X86ISA::IntelMP::BusHierarchy *
-X86IntelMPBusHierarchyParams::create() const
-{
-    return new X86ISA::IntelMP::BusHierarchy(*this);
-}
-
 Addr
 X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
@@ -450,9 +396,3 @@ X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(const Params &p) :
     if (p.add)
         mod |= 1;
 }
-
-X86ISA::IntelMP::CompatAddrSpaceMod *
-X86IntelMPCompatAddrSpaceModParams::create() const
-{
-    return new X86ISA::IntelMP::CompatAddrSpaceMod(*this);
-}

src/arch/x86/bios/smbios.cc

@@ -322,15 +322,3 @@ X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
     intChecksum = -intChecksum;
     proxy.writeBlob(addr + 0x15, &intChecksum, 1);
 }
-
-X86ISA::SMBios::BiosInformation *
-X86SMBiosBiosInformationParams::create() const
-{
-    return new X86ISA::SMBios::BiosInformation(*this);
-}
-
-X86ISA::SMBios::SMBiosTable *
-X86SMBiosSMBiosTableParams::create() const
-{
-    return new X86ISA::SMBios::SMBiosTable(*this);
-}

src/arch/x86/fs_workload.cc

@@ -377,9 +377,3 @@ FsWorkload::writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table)
 }
 
 } // namespace X86ISA
-
-X86ISA::FsWorkload *
-X86FsWorkloadParams::create() const
-{
-    return new X86ISA::FsWorkload(*this);
-}

src/arch/x86/interrupts.cc

@@ -773,12 +773,6 @@ X86ISA::Interrupts::unserialize(CheckpointIn &cp)
     }
 }
 
-X86ISA::Interrupts *
-X86LocalApicParams::create() const
-{
-    return new X86ISA::Interrupts(*this);
-}
-
 void
 X86ISA::Interrupts::processApicTimerEvent()
 {

src/arch/x86/isa.cc

@@ -435,9 +435,3 @@ ISA::setThreadContext(ThreadContext *_tc)
 }
 
 }
-
-X86ISA::ISA *
-X86ISAParams::create() const
-{
-    return new X86ISA::ISA(*this);
-}

src/arch/x86/linux/fs_workload.cc

@@ -128,9 +128,3 @@ FsLinux::initState()
 }
 
 } // namespace X86ISA
-
-X86ISA::FsLinux *
-X86FsLinuxParams::create() const
-{
-    return new X86ISA::FsLinux(*this);
-}

src/arch/x86/linux/se_workload.cc

@@ -169,9 +169,3 @@ EmuLinux::pageFault(ThreadContext *tc)
 }
 
 } // namespace X86ISA
-
-X86ISA::EmuLinux *
-X86EmuLinuxParams::create() const
-{
-    return new X86ISA::EmuLinux(*this);
-}

src/arch/x86/mmu.cc

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2020 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/x86/mmu.hh"
-
-X86ISA::MMU *
-X86MMUParams::create() const
-{
-    return new X86ISA::MMU(*this);
-}

src/arch/x86/nativetrace.cc

@@ -186,13 +186,3 @@ X86NativeTrace::check(NativeTraceRecord *record)
 }
 
 } // namespace Trace
-
-////////////////////////////////////////////////////////////////////////
-//
-//  ExeTracer Simulation Object
-//
-Trace::X86NativeTrace *
-X86NativeTraceParams::create() const
-{
-    return new Trace::X86NativeTrace(*this);
-}

src/arch/x86/pagetable_walker.cc

@@ -736,9 +736,3 @@ Walker::WalkerState::pageFault(bool present)
 }
 
 /* end namespace X86ISA */ }
-
-X86ISA::Walker *
-X86PagetableWalkerParams::create() const
-{
-    return new X86ISA::Walker(*this);
-}

src/arch/x86/tlb.cc

@@ -571,9 +571,3 @@ TLB::getTableWalkerPort()
 }
 
 } // namespace X86ISA
-
-X86ISA::TLB *
-X86TLBParams::create() const
-{
-    return new X86ISA::TLB(*this);
-}

src/base/filters/block_bloom_filter.cc

@@ -90,10 +90,3 @@ Block::hash(Addr addr) const
 }
 
 } // namespace BloomFilter
-
-BloomFilter::Block*
-BloomFilterBlockParams::create() const
-{
-    return new BloomFilter::Block(*this);
-}
-

src/base/filters/bulk_bloom_filter.cc

@@ -96,10 +96,3 @@ Bulk::permute(Addr addr) const
 }
 
 } // namespace BloomFilter
-
-BloomFilter::Bulk*
-BloomFilterBulkParams::create() const
-{
-    return new BloomFilter::Bulk(*this);
-}
-

src/base/filters/h3_bloom_filter.cc

@@ -390,10 +390,3 @@ H3::hash(Addr addr, int hash_number) const
 }
 
 } // namespace BloomFilter
-
-BloomFilter::H3*
-BloomFilterH3Params::create() const
-{
-    return new BloomFilter::H3(*this);
-}
-

src/base/filters/multi_bit_sel_bloom_filter.cc

@@ -95,9 +95,3 @@ MultiBitSel::hash(Addr addr, int hash_number) const
 
 } // namespace BloomFilter
 
-BloomFilter::MultiBitSel*
-BloomFilterMultiBitSelParams::create() const
-{
-    return new BloomFilter::MultiBitSel(*this);
-}
-

src/base/filters/multi_bloom_filter.cc

@@ -110,10 +110,3 @@ Multi::getTotalCount() const
 }
 
 } // namespace BloomFilter
-
-BloomFilter::Multi*
-BloomFilterMultiParams::create() const
-{
-    return new BloomFilter::Multi(*this);
-}
-

src/base/filters/perfect_bloom_filter.cc

@@ -79,10 +79,3 @@ Perfect::getTotalCount() const
 }
 
 } // namespace BloomFilter
-
-BloomFilter::Perfect*
-BloomFilterPerfectParams::create() const
-{
-    return new BloomFilter::Perfect(*this);
-}
-

src/base/vnc/vncinput.cc

@@ -133,10 +133,3 @@ VncInput::captureFrameBuffer()
 
     ++captureCurrentFrame;
 }
-
-// create the VNC Replayer object
-VncInput *
-VncInputParams::create() const
-{
-    return new VncInput(*this);
-}

src/base/vnc/vncserver.cc

@@ -729,11 +729,3 @@ VncServer::frameBufferResized()
             detach();
     }
 }
-
-// create the VNC server object
-VncServer *
-VncServerParams::create() const
-{
-    return new VncServer(*this);
-}
-

src/cpu/SConscript

@@ -119,5 +119,4 @@ Source('timing_expr.cc')
 SimObject('DummyChecker.py')
 SimObject('StaticInstFlags.py')
 Source('checker/cpu.cc')
-Source('dummy_checker.cc')
 DebugFlag('Checker')

src/cpu/dummy_checker.cc

@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2011, 2019 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "cpu/dummy_checker.hh"
-
-#include "params/DummyChecker.hh"
-
-DummyChecker *
-DummyCheckerParams::create() const
-{
-    // The checker should check all instructions executed by the main
-    // cpu and therefore any parameters for early exit don't make much
-    // sense.
-    fatal_if(max_insts_any_thread || max_insts_all_threads ||
-             progress_interval, "Invalid checker parameters");
-
-    return new DummyChecker(*this);
-}

src/cpu/dummy_checker.hh

@@ -39,6 +39,7 @@
 #define __CPU_DUMMY_CHECKER_HH__
 
 #include "cpu/checker/cpu.hh"
+#include "params/DummyChecker.hh"
 
 /**
  * Specific non-templated derived class used for SimObject configuration.
@@ -46,9 +47,15 @@
 class DummyChecker : public CheckerCPU
 {
   public:
-    DummyChecker(const Params &p)
-          : CheckerCPU(p)
-    { }
+    DummyChecker(const Params &p) : CheckerCPU(p)
+    {
+        // The checker should check all instructions executed by the main
+        // cpu and therefore any parameters for early exit don't make much
+        // sense.
+        fatal_if(p.max_insts_any_thread || p.max_insts_all_threads ||
+                 p.progress_interval, "Invalid checker parameters");
+
+    }
 };
 
 #endif // __CPU_DUMMY_CHECKER_HH__

src/cpu/exetrace.cc

@@ -199,13 +199,3 @@ Trace::ExeTracerRecord::dump()
 }
 
 } // namespace Trace
-
-////////////////////////////////////////////////////////////////////////
-//
-//  ExeTracer Simulation Object
-//
-Trace::ExeTracer *
-ExeTracerParams::create() const
-{
-    return new Trace::ExeTracer(*this);
-}

src/cpu/func_unit.cc

@@ -95,38 +95,3 @@ FuncUnit::isPipelined(OpClass capability)
 {
     return pipelined[capability];
 }
-
-////////////////////////////////////////////////////////////////////////////
-//
-//  The SimObjects we use to get the FU information into the simulator
-//
-////////////////////////////////////////////////////////////////////////////
-
-//
-//  We use 2 objects to specify this data in the INI file:
-//    (1) OpDesc - Describes the operation class & latencies
-//                   (multiple OpDesc objects can refer to the same
-//                   operation classes)
-//    (2) FUDesc - Describes the operations available in the unit &
-//                   the number of these units
-//
-//
-
-
-//
-//  The operation-class description object
-//
-OpDesc *
-OpDescParams::create() const
-{
-    return new OpDesc(*this);
-}
-
-//
-//  The FuDesc object
-//
-FUDesc *
-FUDescParams::create() const
-{
-    return new FUDesc(*this);
-}

src/cpu/func_unit.hh

@@ -39,6 +39,22 @@
 #include "params/OpDesc.hh"
 #include "sim/sim_object.hh"
 
+////////////////////////////////////////////////////////////////////////////
+//
+//  The SimObjects we use to get the FU information into the simulator
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+//  We use 2 objects to specify this data in the INI file:
+//    (1) OpDesc - Describes the operation class & latencies
+//                   (multiple OpDesc objects can refer to the same
+//                   operation classes)
+//    (2) FUDesc - Describes the operations available in the unit &
+//                   the number of these units
+//
+//
+
 ////////////////////////////////////////////////////////////////////////////
 //
 //  Structures used ONLY during the initialization phase...

src/cpu/inst_pb_trace.cc

@@ -174,11 +174,3 @@ InstPBTrace::traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f)
 }
 
 } // namespace Trace
-
-
-Trace::InstPBTrace*
-InstPBTraceParams::create() const
-{
-    return new Trace::InstPBTrace(*this);
-}
-

src/cpu/inteltrace.cc

@@ -54,13 +54,3 @@ Trace::IntelTraceRecord::dump()
 }
 
 } // namespace Trace
-
-////////////////////////////////////////////////////////////////////////
-//
-//  ExeTracer Simulation Object
-//
-Trace::IntelTrace *
-IntelTraceParams::create() const
-{
-    return new Trace::IntelTrace(*this);
-}

src/cpu/intr_control.cc

@@ -74,9 +74,3 @@ IntrControl::havePosted(int cpu_id) const
     auto *tc = sys->threads[cpu_id];
     return tc->getCpuPtr()->checkInterrupts(tc->threadId());
 }
-
-IntrControl *
-IntrControlParams::create() const
-{
-    return new IntrControl(*this);
-}

src/cpu/intr_control_noisa.cc

@@ -43,9 +43,3 @@ void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
 }
-
-IntrControl *
-IntrControlParams::create() const
-{
-    return new IntrControl(*this);
-}

src/cpu/kvm/vm.cc

@@ -64,6 +64,12 @@ Kvm *Kvm::instance = NULL;
 Kvm::Kvm()
     : kvmFD(-1), apiVersion(-1), vcpuMMapSize(0)
 {
+    static bool created = false;
+    if (created)
+        warn_once("Use of multiple KvmVMs is currently untested!");
+
+    created = true;
+
     kvmFD = ::open("/dev/kvm", O_RDWR);
     if (kvmFD == -1)
         fatal("KVM: Failed to open /dev/kvm\n");
@@ -579,16 +585,3 @@ KvmVM::ioctl(int request, long p1) const
 
     return ::ioctl(vmFD, request, p1);
 }
-
-
-KvmVM *
-KvmVMParams::create() const
-{
-    static bool created = false;
-    if (created)
-        warn_once("Use of multiple KvmVMs is currently untested!\n");
-
-    created = true;
-
-    return new KvmVM(*this);
-}

src/cpu/kvm/x86_cpu.cc

@@ -1621,9 +1621,3 @@ X86KvmCPU::setVCpuEvents(const struct kvm_vcpu_events &events)
     if (ioctl(KVM_SET_VCPU_EVENTS, (void *)&events) == -1)
         panic("KVM: Failed to set guest debug registers\n");
 }
-
-X86KvmCPU *
-X86KvmCPUParams::create() const
-{
-    return new X86KvmCPU(*this);
-}

src/cpu/minor/cpu.cc

@@ -291,12 +291,6 @@ MinorCPU::wakeupOnEvent(unsigned int stage_id)
     pipeline->start();
 }
 
-MinorCPU *
-MinorCPUParams::create() const
-{
-    return new MinorCPU(*this);
-}
-
 Port &
 MinorCPU::getInstPort()
 {

src/cpu/minor/func_unit.cc

@@ -44,36 +44,6 @@
 #include "debug/MinorTiming.hh"
 #include "enums/OpClass.hh"
 
-MinorOpClass *
-MinorOpClassParams::create() const
-{
-    return new MinorOpClass(*this);
-}
-
-MinorOpClassSet *
-MinorOpClassSetParams::create() const
-{
-    return new MinorOpClassSet(*this);
-}
-
-MinorFUTiming *
-MinorFUTimingParams::create() const
-{
-    return new MinorFUTiming(*this);
-}
-
-MinorFU *
-MinorFUParams::create() const
-{
-    return new MinorFU(*this);
-}
-
-MinorFUPool *
-MinorFUPoolParams::create() const
-{
-    return new MinorFUPool(*this);
-}
-
 MinorOpClassSet::MinorOpClassSet(const MinorOpClassSetParams &params) :
     SimObject(params),
     opClasses(params.opClasses),

src/cpu/o3/SConscript

@@ -38,7 +38,6 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('base_dyn_inst.cc')
     Source('commit.cc')
     Source('cpu.cc')
-    Source('deriv.cc')
     Source('decode.cc')
     Source('dyn_inst.cc')
     Source('fetch.cc')

src/cpu/o3/checker.cc

@@ -41,19 +41,6 @@
 #include "cpu/o3/checker.hh"
 
 #include "cpu/checker/cpu_impl.hh"
-#include "params/O3Checker.hh"
 
 template
 class Checker<O3CPUImpl>;
-
-O3Checker *
-O3CheckerParams::create() const
-{
-    // The checker should check all instructions executed by the main
-    // cpu and therefore any parameters for early exit don't make much
-    // sense.
-    fatal_if(max_insts_any_thread || max_insts_all_threads ||
-             progress_interval, "Invalid checker parameters");
-
-    return new O3Checker(*this);
-}

src/cpu/o3/checker.hh

@@ -51,7 +51,14 @@
 class O3Checker : public Checker<O3CPUImpl>
 {
   public:
-    O3Checker(const Params &p) : Checker<O3CPUImpl>(p) {}
+    O3Checker(const Params &p) : Checker<O3CPUImpl>(p)
+    {
+        // The checker should check all instructions executed by the main
+        // cpu and therefore any parameters for early exit don't make much
+        // sense.
+        fatal_if(p.max_insts_any_thread || p.max_insts_all_threads ||
+                 p.progress_interval, "Invalid checker parameters");
+    }
 };
 
 #endif // __CPU_O3_CHECKER_HH__